公开(公告)号：US12200936B2

公开(公告)日：2025-01-14

申请号：US18492504

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Jee Hoon Han ,  Seo-Goo Kang ,  Hyo Joon Ryu

IPC: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

公开(公告)号：US11910613B2

公开(公告)日：2024-02-20

申请号：US17530220

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon Ryu ,  Hee Suk Kim ,  Jeong Yong Sung ,  Jee Hoon Han

IPC: H10B43/27 ,  H10B43/50 ,  H01L23/522 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device includes a mold structure including a plurality of wordlines on a front side of a first substrate, and a string selection line and a stopper line on the plurality of wordlines. A channel structure extends in a vertical direction to penetrate the mold structure. A block separation area extends in a first direction to cut the mold structure. A protective structure is interposed between the block separation area and the stopper line and not between the block separation area and the string selection line and not between the block separation area and the plurality of wordlines. A string separation structure extends in the first direction to cut the string selection line and the stopper line. A bitline extends in a second direction on the mold structure. A bitline contact connects the channel structure and the bitline.

公开(公告)号：US11864384B2

公开(公告)日：2024-01-02

申请号：US17579656

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk Moon ,  Seo-Goo Kang ,  Young Hwan Son ,  Kohji Kanamori ,  Jee Hoon Han

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US11631692B2

公开(公告)日：2023-04-18

申请号：US16935306

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae Min Lee ,  Shin Hwan Kang ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.

公开(公告)号：US11502101B2

公开(公告)日：2022-11-15

申请号：US17022525

申请日：2020-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Jee Hoon Han ,  Seo-Goo Kang ,  Hyo Joon Ryu

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  G11C8/14 ,  H01L27/11526 ,  H01L27/11556 ,  G11C7/18 ,  H01L27/11519

Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

公开(公告)号：US11233065B2

公开(公告)日：2022-01-25

申请号：US16718498

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk Moon ,  Seo-Goo Kang ,  Young Hwan Son ,  Kohji Kanamori ,  Jee Hoon Han

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US11024638B2

公开(公告)日：2021-06-01

申请号：US16419371

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Il Shim ,  Kyung Dong Kim ,  Ju Hak Song ,  Jee Hoon Han

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

公开(公告)号：US20200303401A1

公开(公告)日：2020-09-24

申请号：US16527506

申请日：2019-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Yong Seok Kim ,  Kyung Hwan Lee ,  Jun Hee Lim ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L23/528 ,  H01L25/18 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  H01L25/00

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.