公开(公告)号：US20080245301A1

公开(公告)日：2008-10-09

申请号：US12140438

申请日：2008-06-17

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: C23C16/00

CPC classification number: C23C16/45546 ,  C23C16/4557 ,  C23C16/45578

Abstract: The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.

Abstract translation: 本发明包括可以在原子层沉积或化学气相沉积期间使用的沉积方法和装置。 加热表面设置在半导体衬底的堆叠和前体入口之间，并且被配置为使得有问题的副反应发生在加热表面附近，而不是靠近半导体衬底。 前体入口可以是多个前体入口之一，并且加热的表面可以是多个加热表面中的一个。

公开(公告)号：US07422635B2

公开(公告)日：2008-09-09

申请号：US10652461

申请日：2003-08-28

Applicant: Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  David J. Kubista ,  Cem Basceri

Inventor： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  David J. Kubista ,  Cem Basceri

IPC: C23C16/00 ,  C23C16/455 ,  H01L21/306

CPC classification number: C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

Abstract translation: 本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。 一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。 第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。 第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。 第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。 第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

公开(公告)号：US07416933B2

公开(公告)日：2008-08-26

申请号：US10913281

申请日：2004-08-06

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.

Abstract translation: 描述了在半导体组件上形成互补晶体管的互补晶体管和方法。 晶体管形成有可选的界面氧化物，例如SiO 2或氧化氮化物，以覆盖将被导电掺杂用于PMOS和NMOS区域的半导体衬底。 然后，在界面氧化物上沉积具有至少七个以上的高介电常数（也称为高k电介质）的电介质。 高k电介质覆盖有从NMOS区域去除的金属氧化物（即，氧化铝，Al 2 O 3 O 3）的薄单层，但保留在 PMOS区域。 所得到的NMOS晶体管扩散区域主要含有金属与硅键，其主要在价带附近产生费米能级钉扎，而所得的PMOS晶体管扩散区域含有金属与硅键，主要在导带附近产生费米能级钉扎。

公开(公告)号：US07407892B2

公开(公告)日：2008-08-05

申请号：US11127945

申请日：2005-05-11

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L21/44 ,  H01L21/31

CPC classification number: C23C16/45546 ,  C23C16/4557 ,  C23C16/45578

Abstract: The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.

Abstract translation: 本发明包括可以在原子层沉积或化学气相沉积期间使用的沉积方法和装置。 加热表面设置在半导体衬底的堆叠和前体入口之间，并且被配置为使得有问题的副反应发生在加热表面附近，而不是靠近半导体衬底。 前体入口可以是多个前体入口之一，并且加热的表面可以是多个加热表面中的一个。

公开(公告)号：US07279398B2

公开(公告)日：2007-10-09

申请号：US11327794

申请日：2006-01-06

Applicant: Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

Inventor： Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/302 ,  H01L21/461 ,  H01L21/469

CPC classification number: C23C16/45527 ,  C23C16/34 ,  C23C16/45546

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract translation: 本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。 一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。 当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。 第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。 在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。 此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

公开(公告)号：US07264768B2

公开(公告)日：2007-09-04

申请号：US11060794

申请日：2005-02-18

Applicant: Mark E. Tuttle ,  Ronald A. Weimer

Inventor： Mark E. Tuttle ,  Ronald A. Weimer

IPC: F24J3/00

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  H01F1/0009 ,  H01F41/304

Abstract: A device for magnetically annealing magnetoresistive elements formed on wafers includes a heated chuck and a delivery mechanism for individually placing the wafers individually on the chuck one at a time. A coil is adjacent to the chuck and generates a magnetic field after the wafer is heated to a Néel temperature of an anti-ferromagnetic layer. A control system regulates the temperature of the heated chuck, the strength of the magnetic field, and a time period during which each chuck is heated to control the annealing process. The annealed elements are incorporated in the fabrication of magnetic memory devices.

Abstract translation: 用于磁性退火在晶片上形成的磁阻元件的装置包括加热的卡盘和用于将晶片单独地单独地放置在卡盘上的输送机构。 线圈与卡盘相邻，并且在将晶片加热到反铁磁层的Néel温度之后产生磁场。 控制系统调节加热卡盘的温度，磁场的强度以及加热每个卡盘以控制退火过程的时间段。 退火元件被结合在磁存储器件的制造中。

公开(公告)号：US07126181B2

公开(公告)日：2006-10-24

申请号：US11003642

申请日：2004-12-03

Applicant: Denise M. Eppich ,  Ronald A. Weimer

Inventor： Denise M. Eppich ,  Ronald A. Weimer

IPC: H01L27/108

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28167 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract translation: 本发明包括形成电路装置的方法。 在导电掺杂的硅和电介质层之间形成包含不大于（或者包括不超过70个ALD循环的厚度）的厚度的含金属材料。 导电掺杂的硅可以是n型硅，并且介电层可以是高k电介质材料。 含金属材料可以直接形成在电介质层上，并且导电掺杂的硅可以直接形成在含金属的材料上。 电路器件可以是电容器结构或晶体管结构。 如果电路器件是晶体管结构，则可以将其并入CMOS组件中。 本发明的各种装置可以结合到存储器结构中，并且可以并入到电子系统中。

公开(公告)号：US07095088B2

公开(公告)日：2006-08-22

申请号：US10859814

申请日：2004-06-03

Applicant: Don Carl Powell ,  Garry Anthony Mercaldi ,  Ronald A. Weimer

Inventor： Don Carl Powell ,  Garry Anthony Mercaldi ,  Ronald A. Weimer

IPC: H01L29/76

CPC classification number: H01L29/513 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02263 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28035 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3125 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L28/57 ,  H01L29/518 ,  H01L2924/19041

Abstract: Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer.

Abstract translation: 公开了利用含硅阻挡层的系统和装置。 公开了半导体器件，并且包括衬底，栅极氧化物，含硅势垒层和栅电极。 栅极氧化物形成在衬底上。 通过使前体层的硅原子与反应剂反应，在栅极氧化物上形成含硅势垒层。 栅电极形成在含硅阻挡层的上方。

公开(公告)号：US06998675B2

公开(公告)日：2006-02-14

申请号：US10871918

申请日：2004-06-18

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L29/788

CPC classification number: B82Y10/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28273 ,  H01L21/3205 ,  H01L29/42324 ,  H01L29/4916

Abstract: The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.

公开(公告)号：US06972223B2

公开(公告)日：2005-12-06

申请号：US09805911

申请日：2001-03-15

Applicant: Ronald A. Weimer ,  Er-Xuan Ping

Inventor： Ronald A. Weimer ,  Er-Xuan Ping

IPC: H01L21/314 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/31 ,  H01L27/108 ,  H01L21/8238

CPC classification number: H01L21/823475 ,  H01L21/3145 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L23/3192 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.

Abstract translation: 公开了一种在玻璃膜和存储器件的有源区之间形成的复合阻挡层。 复合阻挡层包括通过原子沉积工艺形成的氧化物层和形成在氧化物层上的绝缘层，例如氮化物阻挡层。 复合阻挡层消除了杂质原子从玻璃膜扩散到器件的有源区中。