公开(公告)号：US20140353720A1

公开(公告)日：2014-12-04

申请号：US14271277

申请日：2014-05-06

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件具有衬底，其上具有缓冲层，沟道层，阻挡层，穿透其中并到达沟道层内部的沟槽，通过栅极绝缘膜放置在沟槽中的栅电极，以及漏极和源极 位于栅电极两侧的阻挡层上的电极。 栅极绝缘膜具有由第一绝缘膜形成并从沟槽的端部延伸至漏极侧的第一部分和由第一绝缘膜和第二绝缘膜构成的第二部分，并且设置在漏电极侧 相对于第一部分。 可以通过减小在漏电极侧的沟槽的端部处的第一部分的厚度来减小导通电阻。

公开(公告)号：US10896980B2

公开(公告)日：2021-01-19

申请号：US16598832

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Okamoto ,  Nobuo Machida ,  Kenichi Hisada

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US10566183B2

公开(公告)日：2020-02-18

申请号：US16052929

申请日：2018-08-02

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Takashi Ide

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/20

Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.

公开(公告)号：US10134908B2

公开(公告)日：2018-11-20

申请号：US15363386

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto

IPC: H01L29/786 ,  H01L21/30 ,  H01L29/20 ,  H01L29/66

Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

公开(公告)号：US09985108B2

公开(公告)日：2018-05-29

申请号：US14330995

申请日：2014-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Masaaki Kanazawa ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Hironobu Miyamoto ,  Ryohei Nega

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1-x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0

公开(公告)号：US09954087B2

公开(公告)日：2018-04-24

申请号：US14470403

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/15 ,  H01L29/20 ,  H01L29/423 ,  H01L29/205

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≥5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

公开(公告)号：US09748225B2

公开(公告)日：2017-08-29

申请号：US14970627

申请日：2015-12-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao Miura ,  Hironobu Miyamoto ,  Yasuhiro Okamoto

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/872 ,  H01L27/06 ,  H01L23/00 ,  H01L27/02 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/4846 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

公开(公告)号：US20170054014A1

公开(公告)日：2017-02-23

申请号：US15345880

申请日：2016-11-08

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/15 ,  H01L23/522

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

Abstract translation: 半导体器件包括穿透阻挡层的沟槽，并且到达上述形成的n +层，n型层，p型层，沟道层和势垒层中的沟道层的中间部分 基板，通过栅极绝缘膜布置在沟槽内的栅电极，以及形成在栅电极两侧的势垒层上方的源电极和漏电极。 n型层和漏电极通过到达n +层的连接部分电耦合。 p型层和源电极通过到达p型层的连接部电耦合。 在源电极和漏电极之间设置包括p型层和n型层的二极管，从而防止由雪崩击穿引起的元件断裂。

公开(公告)号：US09536978B2

公开(公告)日：2017-01-03

申请号：US14198430

申请日：2014-03-05

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Ryohei Nega ,  Masaaki Kanazawa ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/15 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7787

Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

Abstract translation: 提高半导体器件的性能。 例如，假设超晶格层被插入在缓冲层和沟道层之间，则导入形成超晶格层的一部分的氮化物半导体层中的受主的浓度高于形成氮化物半导体层的受主的浓度 超晶格层的另一部分。 也就是说，导入具有小带隙的氮化物半导体层的受主的浓度高于导入具有大带隙的氮化物半导体层的受主的浓度。

公开(公告)号：US09368609B2

公开(公告)日：2016-06-14

申请号：US14332954

申请日：2014-07-16

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate electrode disposed byway of a gate insulation film in the inside of the trench. Then, the end of the bottom of the trench is in a rounded shape and the gate insulation film in contact with the end of the bottom of the trench is in a rounded shape. By providing the end of the bottom of the trench with a roundness as described above, a thickness of the gate insulation film situated between the end of the bottom of the gate electrode and the end of the bottom of the trench can be decreased. Thus, the channel is formed also at the end of the bottom of the trench to reduce the resistance of the channel.

Abstract translation: 半导体器件具有在衬底上形成的沟道层，形成在沟道层上方并且具有比沟道层大的带隙的势垒层的沟道层，通过阻挡层的沟道至沟道层的中间， 以及在沟槽内部通过栅极绝缘膜设置的栅电极。 然后，沟槽底部的端部为圆形，并且与沟槽底部的端部接触的栅极绝缘膜为圆形。 通过如上所述地提供具有圆度的沟槽底部的端部，可以减小位于栅电极的底部端部和沟槽底部端部之间的栅极绝缘膜的厚度。 因此，沟道也形成在沟槽底部的端部以减小沟道的电阻。