公开(公告)号：US11079539B2

公开(公告)日：2021-08-03

申请号：US16370409

申请日：2019-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/12 ,  H01S5/02345 ,  H01L31/12 ,  H01L31/0232 ,  H01L31/18 ,  H01S5/02326 ,  H01S5/02 ,  H01S5/026 ,  H01S5/40 ,  H01S5/02375 ,  H01S5/042 ,  H01S5/028 ,  H01L31/02

Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.

公开(公告)号：US10720411B2

公开(公告)日：2020-07-21

申请号：US16278927

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba ,  Tetsuya Iida

IPC: H01L27/08 ,  H01L25/065 ,  H02K11/33 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L49/02 ,  H01L23/522

Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.

公开(公告)号：US10204987B2

公开(公告)日：2019-02-12

申请号：US15869023

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Satoshi Eguchi ,  Akio Ichimura ,  Natsuo Yamaguchi ,  Tetsuya Iida

IPC: H01L21/31 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US10141397B2

公开(公告)日：2018-11-27

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio Ichimura ,  Satoshi Eguchi ,  Tetsuya Iida ,  Yuya Abiko

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US09761708B2

公开(公告)日：2017-09-12

申请号：US15146766

申请日：2016-05-04

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L29/7824 ,  H01L21/30625 ,  H01L21/743 ,  H01L21/76243 ,  H01L21/76248 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer formed over the insulating film, a first epitaxial layer formed in an opening of the insulating film in a second region over the supporting substrate, an element isolation region formed between the first semiconductor layer and the first epitaxial layer, and a semiconductor element formed over each of the first semiconductor layer in the first region and the first epitaxial layer in the second region. The first semiconductor layer and the first epitaxial layer is spaced apart from each other by 5 μm or more.

公开(公告)号：US11004830B2

公开(公告)日：2021-05-11

申请号：US16598806

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba ,  Tetsuya Iida

IPC: H01L25/065 ,  H03K17/687 ,  H01L25/00

Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

公开(公告)号：US10386586B2

公开(公告)日：2019-08-20

申请号：US15832795

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/12 ,  G02B6/42 ,  H01S5/022 ,  H01S5/042 ,  H01S5/02 ,  G02B6/30 ,  G02B6/13 ,  H01S5/024

Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.

公开(公告)号：US09972713B2

公开(公告)日：2018-05-15

申请号：US14705057

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Tetsuya Iida ,  Akio Ichimura ,  Yuya Abiko

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

公开(公告)号：US09905644B2

公开(公告)日：2018-02-27

申请号：US14965899

申请日：2015-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Satoshi Eguchi ,  Akio Ichimura ,  Natsuo Yamaguchi ,  Tetsuya Iida

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US09786735B2

公开(公告)日：2017-10-10

申请号：US14968004

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Akio Ichimura ,  Satoshi Eguchi ,  Tetsuya Iida ,  Yuya Abiko

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.