公开(公告)号：US20170059669A1

公开(公告)日：2017-03-02

申请号：US14836860

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Kan ,  Matthias Georg Gottwald ,  Chando Park ,  Seung Hyuk Kang

IPC: G01R33/12 ,  G11C11/16 ,  G11C29/04

CPC classification number: G01R33/1207 ,  G11C11/16 ,  G11C29/006 ,  G11C29/04 ,  G11C29/56016 ,  G11C2029/1206 ,  G11C2029/5002 ,  G11C2029/5602

Abstract: A method and apparatus for testing a magnetic memory device is provided. The method begins when a magnetic field enhancing backing plate is installed in the test fixture. The magnetic field enhancing backing plate may be installed in the wafer chuck of a wafer testing probe station. The magnetic memory device is installed in the test fixture and a magnetic field is applied to the magnetic memory device. The magnetic field may be applied in-plane or perpendicular to the magnetic memory device. The performance of the magnetic memory device may be determined based on the magnetic field applied to the device. The apparatus includes a magnetic field enhancing backing plate adapted to fit a test fixture, possibly in the wafer chuck. The magnetic field enhancing backing plate is fabricated of high permeability magnetic materials, such as low carbon steel, with a thickness based on the magnetic field used in testing.

Abstract translation: 提供一种用于测试磁存储器件的方法和装置。 当将磁场增强背板安装在测试夹具中时，该方法开始。 磁场增强背板可以安装在晶片测试探针台的晶片卡盘中。 磁存储器件安装在测试夹具中，磁场被施加到磁存储器件。 磁场可以面向或垂直于磁存储器件施加。 磁存储器件的性能可以基于施加到器件的磁场来确定。 该装置包括适于装配测试夹具（可能在晶片卡盘中）的磁场增强背板。 磁场增强背板由高磁导率磁性材料（如低碳钢）制成，厚度基于测试中使用的磁场。

公开(公告)号：US09570509B2

公开(公告)日：2017-02-14

申请号：US14609169

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract translation: 半导体器件包括第一磁隧道结（MTJ）器件，第二MTJ器件和顶电极。 第一MTJ装置包括阻挡层。 第二MTJ装置包括阻挡层。 顶部电极耦合到第一MTJ装置和第二MTJ装置。

公开(公告)号：US09548446B2

公开(公告)日：2017-01-17

申请号：US15133018

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Matthias Georg Gottwald ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device in a magnetoresistive random access memory (MRAM) and method of making the same are provided to achieve a high tunneling magnetoresistance (TMR), a high perpendicular magnetic anisotropy (PMA), good data retention, and a high level of thermal stability. The MTJ device includes a first free ferromagnetic layer, a synthetic antiferromagnetic (SAF) coupling layer, and a second free ferromagnetic layer, where the first and second free ferromagnetic layers have opposite magnetic moments.

Abstract translation: 提供磁阻随机存取存储器（MRAM）中的磁隧道结（MTJ）器件及其制造方法，以实现高隧道磁阻（TMR），高垂直磁各向异性（PMA），良好的数据保留和 高水平的热稳定性。 MTJ装置包括第一自由铁磁层，合成反铁磁（SAF）耦合层和第二自由铁磁层，其中第一和第二自由铁磁层具有相反的磁矩。

公开(公告)号：US09324939B2

公开(公告)日：2016-04-26

申请号：US14321516

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Matthias Georg Gottwald ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device in a magnetoresistive random access memory (MRAM) and method of making the same are provided to achieve a high tunneling magnetoresistance (TMR), a high perpendicular magnetic anisotropy (PMA), good data retention, and a high level of thermal stability. The MTJ device includes a first free ferromagnetic layer, a synthetic antiferromagnetic (SAF) coupling layer, and a second free ferromagnetic layer, where the first and second free ferromagnetic layers have opposite magnetic moments.

Abstract translation: 提供磁阻随机存取存储器（MRAM）中的磁隧道结（MTJ）器件及其制造方法，以实现高隧道磁阻（TMR），高垂直磁各向异性（PMA），良好的数据保留和 高水平的热稳定性。 MTJ装置包括第一自由铁磁层，合成反铁磁（SAF）耦合层和第二自由铁磁层，其中第一和第二自由铁磁层具有相反的磁矩。

公开(公告)号：US09269893B2

公开(公告)日：2016-02-23

申请号：US14243324

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Chando Park ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

Abstract translation: 用于制造磁性隧道结（MTJ）装置的多步骤蚀刻技术包括在第一蚀刻步骤中在MTJ装置的第一电极上形成第一导电硬掩模以蚀刻第一电极。 该方法还包括在第一导电硬掩模上形成第二导电硬掩模，用于在第二蚀刻步骤期间蚀刻MTJ装置的磁性层。 间隔层共形沉积在第一导电硬掩模的侧壁上。 第二导电硬掩模沉积在第一导电硬掩模上并与第一导电硬掩模的侧壁上的间隔层对准。

公开(公告)号：US10833254B2

公开(公告)日：2020-11-10

申请号：US16431490

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC: H01L43/06 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01F10/32

Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

公开(公告)号：US10740017B2

公开(公告)日：2020-08-11

申请号：US15963668

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Wei-Chuan Chen ,  Sungryul Kim ,  Adam Edward Newham ,  Seung Hyuk Kang ,  Rashid Ahmed Akbar Attar

IPC: G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372 ,  H04W4/80

Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

公开(公告)号：US20200066968A1

公开(公告)日：2020-02-27

申请号：US16107484

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Sungryul Kim ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  H01L27/22

Abstract: Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.

公开(公告)号：US10483457B1

公开(公告)日：2019-11-19

申请号：US16102941

申请日：2018-08-14

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  G11C11/56 ,  G11C11/18 ,  G11C11/16

Abstract: Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

公开(公告)号：US10460780B2

公开(公告)日：2019-10-29

申请号：US15939923

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.