公开(公告)号：US20140374839A1

公开(公告)日：2014-12-25

申请号：US13925105

申请日：2013-06-24

申请人： International Business Machines Corporation

发明人： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC分类号： H01L27/088 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

摘要翻译： 具有掺杂阱区的半导体器件包括形成在半导体器件的衬底部分上的掺杂衬底层。 掺杂衬底层沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定宽度。 在掺杂衬底层上形成多个翅片，并且在每个鳍片之间形成氧化物衬底层。 至少一个栅极形成在氧化物衬底层上并延伸穿过多个翅片中的至少一个翅片。

公开(公告)号：US20140349088A1

公开(公告)日：2014-11-27

申请号：US14456212

申请日：2014-08-11

申请人： International Business Machines Corporation

发明人： Chiahsun Tseng ,  David V. Horak ,  Chun-chen Yeh ,  Yunpeng Yin

IPC分类号： H01L21/308 ,  H01L21/67

CPC分类号： H01L21/3081 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/67063 ,  Y10T428/24802

摘要： A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.

公开(公告)号：US20140264603A1

公开(公告)日：2014-09-18

申请号：US14036759

申请日：2013-09-25

申请人： International Business Machines Corporation

发明人： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC分类号： H01L27/12

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545

摘要： A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.

摘要翻译： 一种用于形成鳍状场效应晶体管（FinFET）器件的晶体管器件和方法，其中鳍状物的沟道部分在掩埋的氧化硅上，而硅片上的鳍片的源极和漏极部分。 一种示例性方法包括接收具有通过掩埋氧化物（BOX）层与硅衬底电隔离的硅层的晶片。 BOX层与硅层和硅衬底物理接触。 该方法还包括在硅衬底中注入阱并在阱之间形成垂直源和漏极。 垂直的源极和漏极延伸穿过BOX层，鳍片和一部分虚拟栅极。

公开(公告)号：US10147803B2

公开(公告)日：2018-12-04

申请号：US15214851

申请日：2016-07-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40

摘要： A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US10141428B2

公开(公告)日：2018-11-27

申请号：US15464495

申请日：2017-03-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC分类号： H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L21/306 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/8234

摘要： A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

公开(公告)号：US09991255B2

公开(公告)日：2018-06-05

申请号：US14661590

申请日：2015-03-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

发明人： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC分类号： H01L27/088 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

CPC分类号： H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.

公开(公告)号：US20170148790A1

公开(公告)日：2017-05-25

申请号：US15417907

申请日：2017-01-27

申请人： International Business Machines Corporation

发明人： Hong HE ,  Siva Kanakasabapathy ,  Yunpeng Yin ,  Chiahsun Tseng ,  Junli Wang

IPC分类号： H01L27/088 ,  H01L21/265 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

摘要： A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

公开(公告)号：US20170040437A1

公开(公告)日：2017-02-09

申请号：US15298828

申请日：2016-10-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

摘要： A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

摘要翻译： 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US09543407B2

公开(公告)日：2017-01-10

申请号：US14191751

申请日：2014-02-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

摘要： A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

摘要翻译： 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US09484440B2

公开(公告)日：2016-11-01

申请号：US14752095

申请日：2015-06-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

发明人： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

摘要翻译： 具有非合并翅片延伸的半导体器件及其形成方法。 用于形成半导体器件的方法包括在衬底上形成翅片; 在翅片上形成虚拟栅极，留下源极和漏极区域; 在低于周围绝缘体层的表面水平面处蚀刻散热片; 并从蚀刻的翅片外延生长翅片延伸部分。