公开(公告)号：US10134854B2

公开(公告)日：2018-11-20

申请号：US15248676

申请日：2016-08-26

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ho Kyun Ahn ,  Dong Min Kang ,  Yong-Hwan Kwon ,  Dong-Young Kim ,  Seong Il Kim ,  Hae Cheon Kim ,  Eun Soo Nam ,  Jae Won Do ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Sang-Heung Lee ,  Jong Min Lee ,  Jong-Won Lim ,  Hyun Wook Jung ,  Kyu Jun Cho

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.

公开(公告)号：US09634112B2

公开(公告)日：2017-04-25

申请号：US14633984

申请日：2015-02-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Seong-Il Kim ,  Sang Heung Lee ,  Dong Min Kang ,  Chull Won Ju ,  Jae Kyoung Mun

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/201 ,  H01L29/205 ,  H01L21/285

CPC classification number: H01L29/66462 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/28593 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/778 ,  H01L29/7786

Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

公开(公告)号：US09490214B2

公开(公告)日：2016-11-08

申请号：US14845435

申请日：2015-09-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

公开(公告)号：US09159612B2

公开(公告)日：2015-10-13

申请号：US14021269

申请日：2013-09-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。

公开(公告)号：US09012920B2

公开(公告)日：2015-04-21

申请号：US13867328

申请日：2013-04-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chull Won Ju ,  Hae Cheon Kim ,  Hyung Sup Yoon ,  Woo Jin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Jong-Won Lim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong Min Lee ,  Eun Soo Nam

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L23/00

CPC classification number: H01L29/2003 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L29/41758 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014

Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded. By this configuration, it is possible to reduce the process costs by forming the bump on the substrate based on the wafer level, rapidly emit the heat generated from an AlGaN HEMT device by forming the sub source contact pad and the sub drain contact pad of the substrate in the active region, and efficiently emit the heat generated from the AlGaN HEMT device by forming a via hole on the substrate and filling the via hole with the conductive metal.

Abstract translation: 公开了一种GaN（氮化镓）复合功率半导体器件及其制造方法。 氮化镓化合物功率半导体器件包括：通过在晶片上生长形成的氮化镓复合元素; 包括源极，漏极和与氮化镓复合元件连接的栅极的接触焊盘; 将氮化镓化合物元件倒装芯片接合的模块基板; 形成在所述模块基板上的焊盘; 以及形成在模块基板的焊盘上的凸点，使得接触焊盘和焊盘被倒装芯片接合。 通过这种结构，可以通过基于晶片级在基板上形成凸块来降低处理成本，通过形成子源接触焊盘和子漏极接触焊盘，快速地发射由AlGaN HEMT器件产生的热量 衬底，并且通过在衬底上形成通孔并用导电金属填充通孔，从而有效地发射由AlGaN HEMT器件产生的热量。

公开(公告)号：US08841969B2

公开(公告)日：2014-09-23

申请号：US13670016

申请日：2012-11-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang-Heung Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Chull Won Ju ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H03G3/12

CPC classification number: H03G1/0082 ,  H03G1/0088 ,  H03G3/3084

Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.

Abstract translation: 公开了一种自动增益控制反馈放大器，其即使当输入信号的差异大时也可以任意地控制增益。 自动增益控制反馈放大器包括：放大电路单元，被配置为放大从输入端输入的电压，并将放大的电压输出到输出端; 连接在输入端子和输出端子之间的反馈电路单元，包括反馈电阻器单元，其总电阻值由一个或多个控制信号确定，反馈晶体管并联连接到反馈电阻器单元; 以及偏置电路单元，被配置为向所述反馈晶体管提供预定的偏置电压。

公开(公告)号：US20140167070A1

公开(公告)日：2014-06-19

申请号：US13938324

申请日：2013-07-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Rak PARK ,  Sang Choon Ko ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Sung-Bum Bae ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L29/16 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L23/5225 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。

公开(公告)号：US20140160689A1

公开(公告)日：2014-06-12

申请号：US13959666

申请日：2013-08-05

Applicant: Electronics and Telecommunications Research Institute

Inventor： Dong Min KANG ,  Chull Won Ju ,  Seong-Il Kim ,  Sang-Heung Lee ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49844 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package includes a ground plate, a chip mounting plate disposed at a side of the ground plate and having a top surface lower than a top surface of the ground plate, a chip on the chip mounting plate, a first input/output terminal opposite to the chip mounting plate and disposed at another side of the ground plate, and a second input/output terminal opposite to the ground plate and disposed at a side of the chip mounting plate. The first and second input/output terminals are electrically connected to the chip.

Abstract translation: 一种封装，包括接地板，设置在接地板一侧的芯片安装板，具有比接地板的顶表面低的顶表面，芯片安装板上的芯片，与第一输入/输出端子相对的第一输入/输出端子 芯片安装板并且设置在接地板的另一侧，以及与接地板相对的第二输入/输出端子，并且设置在芯片安装板的一侧。 第一和第二输入/输出端子与芯片电连接。