公开(公告)号：US07684205B2

公开(公告)日：2010-03-23

申请号：US11358723

申请日：2006-02-22

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： H01R9/00

CPC分类号： H05K3/3436 ,  H05K1/0271 ,  H05K3/3426 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49171 ,  Y10T29/49176

摘要： The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.

公开(公告)号：US07614341B1

公开(公告)日：2009-11-10

申请号：US11076422

申请日：2005-03-10

申请人： Deepak K. Pai ,  Scott P. Lichtenauer

发明人： Deepak K. Pai ,  Scott P. Lichtenauer

IPC分类号： B05C17/10

CPC分类号： H05K3/1233 ,  B41F15/46 ,  H05K3/3484 ,  H05K2203/0139

摘要： The present invention relates to a segmented squeegee for depositing a medium onto a surface, such as depositing solder paste onto a printed wiring board. The segmented squeegee may include a plurality of independent squeegee segments or elements, a support structure and a plurality of independent connections or linkages connecting the squeegee segments to the support structure. The segmented squeegee may be used in connection with a conventional stencil such that the independent linkages and the squeegee segments may be structured and arranged to maintain substantial contact between the stencil and the printed wiring board.

摘要翻译： 本发明涉及用于将介质沉积到表面上的分段刮板，例如将焊膏沉积到印刷线路板上。 分段刮板可以包括多个独立的刮板段或元件，支撑结构以及将刮板段连接到支撑结构的多个独立连接或连接。 分段刮板可以与常规模板结合使用，使得独立连杆和刮板段可被构造和布置成保持模板和印刷线路板之间的实质接触。

公开(公告)号：US20090151158A1

公开(公告)日：2009-06-18

申请号：US12379156

申请日：2009-02-13

申请人： Deepak K. Pai ,  Ronald R. Denny

发明人： Deepak K. Pai ,  Ronald R. Denny

IPC分类号： H05K3/36 ,  H05K3/34

CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

摘要： The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

公开(公告)号：US5734475A

公开(公告)日：1998-03-31

申请号：US730096

申请日：1996-10-15

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： G01B11/30 ,  H05K13/08

CPC分类号： H05K13/08 ,  G01B11/306

摘要： A process of measuring coplanarity of an array of conductive elements on a circuit device is disclosed. Light is impinged from a reference plane onto an element of the array at a predetermined angle of incidence. Light is also impinged from the reference plane onto a reflective feature on a measurement plane determined by three points of the circuit device having highest elevations from a base of the circuit device, at the same predetermined angle of incidence. A response of the light impinged onto the element of the array and the reflective feature on the measurement plane is measured to determine coplanarity of the array.

摘要翻译： 公开了一种测量电路器件上导电元件阵列的共面性的工艺。 光以参考平面以预定的入射角撞击到阵列的元件上。 光也从参考平面入射到由电路装置的底部具有最高高度的电路装置的三个点确定的测量平面上的反射特征，并以相同的预定入射角入射。 测量入射到阵列的元件上的光和测量平面上的反射特征的响应，以确定阵列的共面性。

公开(公告)号：US5399239A

公开(公告)日：1995-03-21

申请号：US992620

申请日：1992-12-18

申请人： Deepak K. Pai ,  Lowell D. Lund

发明人： Deepak K. Pai ,  Lowell D. Lund

IPC分类号： H01L21/48 ,  H05K1/05 ,  H05K3/44 ,  H05K3/46 ,  H01L21/00

CPC分类号： H05K3/44 ,  H01L21/4857 ,  H05K1/056 ,  H05K2201/0317 ,  H05K2203/0361 ,  H05K2203/1388 ,  H05K3/467

摘要： The present invention is an integrated heat sink module and a method of fabricating conductive structures on a substrate. The method of the present invention includes cleaning a substrate material to remove any impurities present on the substrate surface. The method further includes placing a protective layer resilient to chemicals used in conductive structure formation, on a first surface. The first surface is opposite a second surface on which conductive structures are formed. The method includes forming conductive structures on the second surface of the substrate. The protective layer is then removed from the first surface of the substrate.

摘要翻译： 本发明是集成散热器模块和在基板上制造导电结构的方法。 本发明的方法包括清洗衬底材料以除去存在于衬底表面上的任何杂质。 该方法还包括在第一表面上放置一个对导电结构形成中使用的化学物质具有弹性的保护层。 第一表面与其上形成导电结构的第二表面相对。 该方法包括在衬底的第二表面上形成导电结构。 然后从衬底的第一表面去除保护层。

公开(公告)号：US4905371A

公开(公告)日：1990-03-06

申请号：US237586

申请日：1988-08-26

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： H05K1/02 ,  H05K3/26 ,  H05K3/34 ,  H05K3/38

CPC分类号： H05K1/0269 ,  H05K2201/0108 ,  H05K2201/10204 ,  H05K3/26 ,  H05K3/341 ,  H05K3/388 ,  Y10T29/49144

摘要： An apparatus and method for a cleaning process control is disclosed. The apparatus includes a printed wire circuit board that is made on a Pyrex glass or other transparent substrate. Components are attached to the printed wire circuit board and then the circuit card assembly which is formed is cleaned using a selected cleaning process. The circuit card assembly can then be inspected to determine the effectiveness of a particular cleaning process by flipping over the transparent circuit card, peering through the substrate to inspect for corrosion and solder balls. The circuit card assembly can then be cleaned more extensively and used again to check a different cleaning process.

摘要翻译： 公开了一种用于清洁过程控制的装置和方法。 该装置包括制造在Pyrex玻璃或其它透明基板上的印刷线路板。 组件附接到印刷线路板上，然后使用选择的清洁过程清洁形成的电路卡组件。 然后可以检查电路卡组件，以通过翻转透明电路卡来确定特定清洁过程的有效性，通过基板对准以检查腐蚀和焊球。 然后可以更广泛地清洁电路卡组件，并再次使用以检查不同的清洁过程。

公开(公告)号：US08549737B2

公开(公告)日：2013-10-08

申请号：US12659777

申请日：2010-03-22

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： H05K3/00

CPC分类号： H05K3/3436 ,  H05K1/0271 ,  H05K3/3426 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49171 ,  Y10T29/49176

摘要： The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.

摘要翻译： 本发明涉及一种用于将球栅阵列封装弹性地连接并电连接到电路板的柔性引线插入器。 插入器可以包括基板，多个焊盘和多个引脚。 多个焊盘可以基本上位于衬底的顶表面上并且以基本上对应于球栅阵列封装上的焊球图案的预定图案布置。 多个销可以被定位成基本上垂直于衬底并且可以延伸通过衬底和多个衬垫。 插入器可以被配置为将球栅阵列封装附接到电路板，使得球栅阵列封装上的每个焊球接触多个引脚和多个焊盘的至少一部分的至少一部分， 多个引脚中的每一个也连接到电路板上的触点。

公开(公告)号：US08481862B2

公开(公告)日：2013-07-09

申请号：US11350276

申请日：2006-02-09

申请人： Deepak K. Pai ,  Melvin Eric Graf

发明人： Deepak K. Pai ,  Melvin Eric Graf

IPC分类号： H05K1/16

CPC分类号： H05K3/3426 ,  H01L23/49811 ,  H01L24/72 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/351 ,  H05K2201/0373 ,  H05K2201/10727 ,  H05K2201/10818 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00

摘要： The present invention relates to a connector system for resiliently attaching and electrically connecting an integrated circuit chip to a circuit board using a plurality of leads. Each of the plurality of leads are sized and arranged to form a curved body having a first leg and a second leg with a curved portion between the first leg and the second leg. The curved body of the leads may be C-shaped in accordance with the present invention. The plurality of leads may be formed from strips of copper foil or copper mesh folded to form the curved body. The plurality of leads may also be sized and arranged to support the integrated circuit chip in a generally flat arrangement relative to the circuit board with a maximum separation of about 0.016 inches or less between the integrated circuit chip and the circuit board.

摘要翻译： 连接器系统技术领域本发明涉及一种使用多根引线将集成电路芯片弹性连接并电连接到电路板的连接器系统。 多个引线中的每一个的尺寸和布置成形成具有第一腿部和第二腿部的弯曲主体，第一腿部和第二腿部之间具有在第一腿部和第二腿部之间的弯曲部分。 根据本发明，引线的弯曲体可以是C形。 多个引线可以由折叠的铜箔或铜网的条形成，以形成弯曲体。 多个引线还可以被设计和布置成将集成电路芯片相对于电路板以大致平坦的布置支撑，在集成电路芯片和电路板之间具有大约0.016英寸或更小的最大间隔。

公开(公告)号：US20100175248A1

公开(公告)日：2010-07-15

申请号：US12659777

申请日：2010-03-22

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： H05K3/34

CPC分类号： H05K3/3436 ,  H05K1/0271 ,  H05K3/3426 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49171 ,  Y10T29/49176

摘要： The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.

摘要翻译： 本发明涉及一种用于将球栅阵列封装弹性地连接并电连接到电路板的柔性引线插入器。 插入器可以包括基板，多个焊盘和多个引脚。 多个焊盘可以基本上位于衬底的顶表面上并且以基本上对应于球栅阵列封装上的焊球图案的预定图案布置。 多个销可以被定位成基本上垂直于衬底并且可以延伸通过衬底和多个衬垫。 插入器可以被配置为将球栅阵列封装附接到电路板，使得球栅阵列封装上的每个焊球接触多个引脚和多个焊盘的至少一部分的至少一部分， 多个引脚中的每一个也连接到电路板上的触点。

公开(公告)号：US06830177B2

公开(公告)日：2004-12-14

申请号：US10238118

申请日：2002-09-10

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： B23K3102

CPC分类号： H01L23/49827 ,  H01L2224/16 ,  H05K3/3421 ,  H05K3/3484 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10719 ,  Y02P70/613

摘要： The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect area grid array chip scale packages (“CSPs”) to printed wiring boards (“PWBs”). The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the corresponding connecting surfaces of the area grid array CSP. Next, the securing tie bars and the tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB. The opposite end of each compliant micro-lead is then electrically connected and mechanically secured to its corresponding connecting pad located on the surface of the PWB, thereby establishing a compliant electrical connection between the area grid array CSP and the PWB. An alternative embodiment of the present invention utilizes an area grid array interposer with compliant micro-leads to provide additional compliancy.

摘要翻译： 本发明包括成本有效的制造，导电和机械兼容的微引线以及利用这些柔性微引线将区域格栅阵列芯片级封装（“CSP”）互连到印刷电路板（“PWB”）的方法。 优选的方法包括使多个导电柔性微引线定向成与导杆和工具平行地彼此固定，以与沿着区域栅格阵列CSP的表面定位的导电焊盘的对应图案对准。 柔性微引线电连接并机械固定到区域网格阵列CSP的对应连接表面。 接下来，拆下固定连接杆和工具。 然后将导电顺应性微引线的相对端定向成与P​​WB上的导电表面焊盘的相应图案对准。 然后，每个柔性微引线的相对端电连接并机械固定到位于PWB表面上的相应的连接焊盘，从而在区域栅格阵列CSP和PWB之间建立顺从的电连接。 本发明的替代实施例利用具有柔性微引线的区域栅格阵列插入器来提供额外的符合性。