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    Laminated multiple substrates
    1.
    发明授权
    Laminated multiple substrates 有权
    层压多个基板

    公开(公告)号：US07282787B2

    公开(公告)日：2007-10-16

    申请号：US10828178

    申请日：2004-04-21

    申请人： Deepak K. Pai ,  Ronald R. Denny

    发明人： Deepak K. Pai ,  Ronald R. Denny

    IPC分类号： H01L23/02

    CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

    摘要： The present invention is for laminated and interconnected multiple substrates forming a multilayer package or other circuit component. A solder bump may be situated on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates pressed together via the adhesive films are mechanically bonded. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

    摘要翻译： 本发明是用于层叠和互连的多个基板，形成多层封装或其他电路部件。 焊料凸块可以位于两个或更多个衬底中的至少一个衬底的导电焊盘上。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 通过粘合剂膜压合在一起的两个或多个基材被机械粘合。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

    Process for manufacturing laminated high layer count printed circuit boards
    2.
    发明授权
    Process for manufacturing laminated high layer count printed circuit boards 失效
    层叠高层数印刷电路板的制造工艺

    公开(公告)号：US06742247B2

    公开(公告)日：2004-06-01

    申请号：US10387871

    申请日：2003-03-14

    申请人： Deepak K. Pai ,  Ronald R. Denny

    发明人： Deepak K. Pai ,  Ronald R. Denny

    IPC分类号： H05K300

    CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

    摘要： The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.

    摘要翻译： 本发明提供了用于层叠和互连多个高层计数（HLC）衬底以形成多层封装或其它电路部件的多种技术。 可以在两个HLC衬底中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的HLC衬底的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将HLC基底压在一起以经由粘合剂机械地粘合两个基底。 在叠层期间或之后可以回流焊料凸点，以产生焊接段，该焊料段通过粘合膜中的孔提供两个导电焊盘之间的电连接。

    Method for forming laminated multiple substrates
    4.
    发明授权
    Method for forming laminated multiple substrates 有权
    层压多层基板的形成方法

    公开(公告)号：US08028403B2

    公开(公告)日：2011-10-04

    申请号：US12379156

    申请日：2009-02-13

    申请人： Deepak K. Pai ,  Ronald R. Denny

    发明人： Deepak K. Pai ,  Ronald R. Denny

    IPC分类号： H05K3/36 ,  B23K31/00

    CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

    摘要： The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

    摘要翻译： 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

    Apparatus and methods of attaching hybrid vlsi chips to printed wiring boards
    6.
    发明申请
    Apparatus and methods of attaching hybrid vlsi chips to printed wiring boards 审中-公开
    将混合型vlsi芯片连接到印刷电路板的装置和方法

    公开(公告)号：US20090250506A1

    公开(公告)日：2009-10-08

    申请号：US12379524

    申请日：2009-02-24

    申请人： Deepak K. Pai

    发明人： Deepak K. Pai

    IPC分类号： B23K1/20

    CPC分类号： H05K3/341 ,  H01L23/4822 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

    摘要： A method for preparing an integrated circuit for connection to a surface, the integrated circuit including lead contacts and leadless contacts, is provided. The method includes providing the integrated circuit, applying a first solder paste to the leadless contacts, forming solder balls on the applied solder paste, heating the solder balls, thereby removing at least a portion of the first solder paste and bringing the solder balls into electrical contact with the leadless contacts, the base of the solder balls being generally aligned in a plane, and bending the lead contacts into gull wings, with the base of the gull wings being substantially coplanar with the plane. The base of the gull wings and the base of the at least one of the solder balls collectively generally define a contact plane for potential future contact with the surface.

    摘要翻译： 提供了一种用于制备用于连接到表面的集成电路的方法，所述集成电路包括引线触点和无引线触点。 该方法包括提供集成电路，将第一焊膏施加到无引线触点，在所施加的焊膏上形成焊球，加热焊球，从而去除至少一部分第一焊膏并使焊球进入电 与无引线触点接触，焊球的基部通常在平面中对准，并且将引线触点弯曲成鸥翼，鸥翼的基部与平面基本上共面。 鸥翼的基部和至少一个焊球的基部通常限定接触平面，以便将来与表面接触。

    Optical fiber cable to inject or extract light
    7.
    发明申请
    Optical fiber cable to inject or extract light 有权
    光纤电缆注入或提取光

    公开(公告)号：US20070193772A1

    公开(公告)日：2007-08-23

    申请号：US11358723

    申请日：2006-02-22

    申请人： Deepak K. Pai

    发明人： Deepak K. Pai

    IPC分类号： H05K1/16

    CPC分类号： H05K3/3436 ,  H05K1/0271 ,  H05K3/3426 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49171 ,  Y10T29/49176

    摘要： The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.

    摘要翻译： 本发明涉及一种用于将球栅阵列封装弹性地连接并电连接到电路板的柔性引线插入器。 插入器可以包括基板，多个焊盘和多个引脚。 多个焊盘可以基本上位于衬底的顶表面上并且以基本上对应于球栅阵列封装上的焊球图案的预定图案布置。 多个销可以被定位成基本上垂直于衬底并且可以延伸通过衬底和多个衬垫。 插入器可以被配置为将球栅阵列封装附接到电路板，使得球栅阵列封装上的每个焊球接触多个引脚和多个焊盘的至少一部分的至少一部分， 多个引脚中的每一个也连接到电路板上的触点。

    Mask alignment mark system
    8.
    发明授权
    Mask alignment mark system 失效
    面罩对准标记系统

    公开(公告)号：US5407763A

    公开(公告)日：1995-04-18

    申请号：US889667

    申请日：1992-05-28

    申请人： Deepak K. Pai

    发明人： Deepak K. Pai

    IPC分类号： G03F9/00

    CPC分类号： G03F9/70 ,  Y10S438/975

    摘要： An alignment mark system and method of using the same wherein each mask of a sequence of masks includes a mask sequence indicium, a first alignment feature and a second alignment feature spaced from the first alignment feature. Each of the mask sequence indicium, the first alignment feature and the second alignment feature produce a corresponding structure as a result of the photolithographic process. The structure resulting from the second alignment feature is aligned with the first alignment feature of the immediately succeeding mask for proper alignment of the mask sequence.

    摘要翻译： 一种对准标记系统及其使用方法，其中掩模序列的每个掩模包括掩模序列标记，第一对准特征和与第一对准特征间隔开的第二对准特征。 作为光刻工艺的结果，掩模序列标记，第一对准特征和第二对准特征中的每一个产生相应的结构。 由第二对准特征产生的结构与紧随其后的掩模的第一对准特征对齐，用于掩模序列的正确对准。

    Method and apparatus to change solder pad size using a differential pad plating
    10.
    发明授权
    Method and apparatus to change solder pad size using a differential pad plating 失效
    使用差分焊盘电镀改变焊盘尺寸的方法和装置

    公开(公告)号：US07892441B2

    公开(公告)日：2011-02-22

    申请号：US11806598

    申请日：2007-06-01

    申请人： Deepak K. Pai

    发明人： Deepak K. Pai

    IPC分类号： H01B13/00 ,  H01K3/10

    CPC分类号： H05K3/4007 ,  H01L21/486 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/113 ,  H05K2201/0394 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49165 ,  H01L2224/0401

    摘要： A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps.

    摘要翻译： 提供一种制造插入件的方法，包括以下步骤：提供具有铜层和聚酰亚胺层的片材，在聚酰亚胺层中的铜层下方的激光钻孔，用铜填充孔并将铜延伸到聚酰亚胺层上方 以限定帽，去除铜层的部分以形成导电焊盘，以及用绝缘体填充导电焊盘之间的间隙，其中各个导电焊盘与相应的单独盖电接触。