公开(公告)号：US10651211B2

公开(公告)日：2020-05-12

申请号：US15309949

申请日：2016-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Chien Hung Liu

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786

Abstract: A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

公开(公告)号：US10416515B2

公开(公告)日：2019-09-17

申请号：US15567207

申请日：2017-04-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1368

Abstract: Pixel unit, array substrate, and display device, and their fabrication methods are provided. The disclosed pixel unit can include: a transistor, including a drain electrode; a pixel electrode, including a first bottom conductive layer in contact with a surface of the drain electrode and a metal layer; and a planarization layer, formed on the transistor and the first bottom conductive layer. The metal layer is electrically connected to the first bottom conductive layer through a via-hole in the planarization layer.

公开(公告)号：US10304856B2

公开(公告)日：2019-05-28

申请号：US15529963

申请日：2016-09-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Yuqing Yang ,  Lujiang Huangfu

IPC: H01L27/12 ,  H01L21/77 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments of the present invention provides an array substrate. The array substrate includes a display region and a packaging region. The packaging region includes a plurality of functional layers. And the packaging region further includes: a plurality of through holes running through at least one of the plurality of functional layers and configured to allow a packaging adhesive to enter therein; and a groove formed above at least some of the through holes, wherein, projection areas of the at least some of the through holes onto a base substrate of the array substrate are located within a projection area of the groove onto the base substrate. Embodiments of the present invention further provides a display panel and a display apparatus including the abovementioned array substrate, and a method of manufacturing the abovementioned array substrate.

公开(公告)号：US09991295B2

公开(公告)日：2018-06-05

申请号：US14772677

申请日：2014-11-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Zuqiang Wang

IPC: H01L21/00 ,  H01L27/12 ,  H01L49/02 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L51/52 ,  H01L21/02 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L21/02043 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L27/124 ,  H01L27/127 ,  H01L27/3244 ,  H01L28/60 ,  H01L29/401 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78672 ,  H01L51/5215 ,  H01L2227/323

Abstract: An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (TFTs) and conductive electrodes; the TFT includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode. With improved layer structures of the array substrate, a plurality of layer structures is formed in one patterning process by stepped photoresist process, so as to reduce the frequency of patterning processes, better ensure the compactness of the array substrate, and guarantee good contact between the layer structures in the array substrate.

公开(公告)号：US09887213B2

公开(公告)日：2018-02-06

申请号：US15125786

申请日：2015-08-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Zuqiang Wang ,  Chien Hung Liu ,  Yu Cheng Chan ,  Lujiang Huangfu

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L21/02675 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78675

Abstract: The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

公开(公告)号：US09589991B2

公开(公告)日：2017-03-07

申请号：US14769180

申请日：2014-12-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zuqiang Wang ,  Chien Hung Liu

IPC: H01L21/31 ,  H01L23/58 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/06 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/786

Abstract: A thin-film transistor (TFT), a manufacturing method thereof, display substrate and a display device are disclosed. The TFT includes: an active layer, gate insulating layer, gate electrode, interlayer dielectric layer, source electrode and a drain electrode disposed on a base substrate in sequence. The source electrode and drain electrode are respectively connected with the active layer via a through hole exposing the active layer; the gate insulating layer at least includes a silicon oxide layer and a silicon nitride layer in a two-layer structure; the interlayer dielectric layer at least includes silicon oxide layers and silicon nitride layers in a four-layer structure; the silicon oxide layers and silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and the dimension of one side of the through hole away from the base substrate is greater than that of one side close to the base substrate.

Abstract translation: 公开了薄膜晶体管（TFT），其制造方法，显示基板和显示装置。 TFT包括：有源层，栅极绝缘层，栅电极，层间介质层，源电极和漏电极，依次设置在基底基板上。 源电极和漏极分别通过暴露有源层的通孔与有源层连接; 栅极绝缘层至少包括二层结构的氧化硅层和氮化硅层; 层间绝缘层至少包括四层结构的氧化硅层和氮化硅层; 栅极绝缘层和层间电介质层的氧化硅层和氮化硅层交替排列; 并且通孔的远离基底的一侧的尺寸大于靠近基底的一侧的尺寸。

公开(公告)号：US09520420B2

公开(公告)日：2016-12-13

申请号：US14402532

申请日：2013-12-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Jangsoon Im ,  Zuqiang Wang

IPC: H01L27/12

CPC classification number: H01L27/1274 ,  H01L27/1255 ,  H01L27/1262

Abstract: The present invention provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing an array substrate, including a step of forming a thin film transistor and a storage capacitor on a substrate, the thin film transistor including a gate, a source, and a drain, and the storage capacitor including a first pole plate and a second pole plate, wherein, arranging the source, the drain, and the first pole plate in a single layer through implanting dopant ions into an amorphous silicon layer formed on the substrate by one ion-implantation process, and through crystallizing an amorphous silicon material forming the amorphous silicon layer and activating the dopant ions by a laser irradiation process. Accordingly, process steps are simplified and a process cost is reduced greatly, and the performances of the array substrate and the display device are increased.

Abstract translation: 本发明提供一种阵列基板，阵列基板和显示装置的制造方法。 制造阵列基板的方法，包括在基板上形成薄膜晶体管和存储电容的步骤，所述薄膜晶体管包括栅极，源极和漏极，所述存储电容器包括第一极板和 第二极板，其中，通过一个离子注入工艺将源极，漏极和第一极板设置在单层中，通过将掺杂剂离子注入到形成在衬底上的非晶硅层中，并且通过使非晶硅材料结晶 形成非晶硅层并通过激光照射工艺激活掺杂剂离子。 因此，简化了处理步骤，并且大大降低了处理成本，并且增加了阵列基板和显示装置的性能。

公开(公告)号：US20160268320A1

公开(公告)日：2016-09-15

申请号：US14772677

申请日：2014-11-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Zuqiang Wang

IPC: H01L27/12 ,  H01L29/40 ,  H01L29/49 ,  H01L49/02 ,  H01L51/52 ,  H01L29/786 ,  H01L29/45

CPC classification number: H01L27/1288 ,  H01L21/02043 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L27/124 ,  H01L27/127 ,  H01L27/3244 ,  H01L28/60 ,  H01L29/401 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78672 ,  H01L51/5215 ,  H01L2227/323

Abstract: An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (TFTs) and conductive electrodes; the TFT includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode. With improved layer structures of the array substrate, a plurality of layer structures is formed in one patterning process by stepped photoresist process, so as to reduce the frequency of patterning processes, better ensure the compactness of the array substrate, and guarantee good contact between the layer structures in the array substrate.

Abstract translation: 提供阵列基板，其制造方法和显示装置。 阵列基板包括薄膜晶体管（TFT）和导电电极; TFT包括栅电极，源电极，漏电极和有源层; 源电极和漏极布置在有源层的相同层和两端，并且至少直接部分地接触有源层的上表面或下表面; 并且导电电极直接设置在电极上。 通过改善阵列基板的层结构，通过阶梯式光刻胶工艺在一个图案化工艺中形成多个层结构，从而降低图案化工艺的频率，更好地确保阵列基板的紧凑性，并保证阵列基板之间的良好接触 阵列基板中的层结构。

公开(公告)号：US20160268319A1

公开(公告)日：2016-09-15

申请号：US14769891

申请日：2014-09-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yinan Liang ,  Zheng Liu ,  Zuqiang Wang ,  Xueyan Tian

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L27/1255 ,  H01L27/3262 ,  H01L2227/323

Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

Abstract translation: 本公开内容提供了一种低温多晶硅场效应TFT阵列基板及其制造方法和显示装置。 该方法：在一个光刻工艺中，使用阶梯式光刻胶工艺在衬底上同时形成多晶硅存储电容器的多晶硅有源层和下极板; 在多晶硅有源层和多晶硅储存电容器的下极板上形成栅极绝缘层; 在所述栅极绝缘层上形成金属层，并蚀刻所述金属层以形成与所述栅电极，源电极，漏电极以及与所述源电极和所述漏极连接的数据线连接的栅电极和栅极线; 依次形成钝化层，光致抗蚀剂层和像素电极层，并在一个光刻工艺中图案化钝化层，光致抗蚀剂层和像素电极层以形成层间绝缘层通孔和像素电极的图案; 在像素电极上形成像素定义层。 本公开可以减少低温多晶硅场效应晶体管阵列基板的光刻工艺的时间，提高产量并降低成本。

公开(公告)号：US20150206905A1

公开(公告)日：2015-07-23

申请号：US14345344

申请日：2013-11-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Zuqiang Wang

IPC: H01L27/12 ,  H01L21/324 ,  H01L21/265 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

Abstract: A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

Abstract translation: 多晶硅薄膜晶体管及其制造方法，阵列基板涉及显示技术领域，可以修复多晶硅中的边界缺陷和缺陷状态，抑制热载流子效应，使TFT的特性更加稳定。 多晶硅薄膜晶体管包括栅电极，源电极，漏电极和有源层，有源层至少包括沟道区，第一掺杂区，第二掺杂区和重掺杂区，第一掺杂区是 设置在通道区域的两侧，第二掺杂区域设置在远离通道区域的第一掺杂区域的侧面上; 重掺杂区域设置在与第一掺杂区域相对的第二掺杂区域的侧面上; 并且重掺杂区域中的离子的剂量位于第一掺杂区域和第二掺杂区域中的离子剂量。