公开(公告)号：US20240194698A1

公开(公告)日：2024-06-13

申请号：US17772395

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Binbin Tong ,  Zhen Zhang ,  Zhenyu Zhang ,  Fuqiang Li ,  Chengfu Xu

IPC: H01L27/12

CPC classification number: H01L27/1251 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/127

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes an active area and a non-active area located at the periphery of the active area, wherein the active area includes an opening area and a non-opening area. The displaying base plate includes a substrate and a thin-film transistor disposed on one side of the substrate, wherein the thin-film transistor includes a grid electrode, an active layer, a source-drain electrode and an auxiliary film layer, an excavation area is disposed on the auxiliary film layer, and an orthographic projection of the excavation area on the substrate at least partially covers the opening area.

公开(公告)号：US11996017B2

公开(公告)日：2024-05-28

申请号：US17508866

申请日：2021-10-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shuilang Dong ,  Xinhong Lu ,  Jingshang Zhou ,  Lei Zhao ,  Zhanfeng Cao ,  Dapeng Xue ,  Lizhong Wang ,  Guangcai Yuan

IPC: H01L33/62 ,  G09F9/302 ,  G09F9/33 ,  H10K77/10

CPC classification number: G09F9/3026 ,  G09F9/33 ,  H01L33/62 ,  H10K77/111

Abstract: The present application discloses an array substrate and a splicing screen. The array substrate provided by an embodiment of the present application includes: a flexible base, wherein the flexible base includes a display region, a first region and a second region, the display region and at least one of the first region and the second region are located in different planes, and the first region is located between the display region and the second region; a plurality of signal lines, arranged on the display region and the first region; a plurality of fan-out lines, arranged on the second region and connected with the plurality of signal lines in a one-to-one correspondence; and a buffer cushion, arranged on the first region, wherein an orthographic projection of the buffer cushion on the flexible base does not overlap with orthographic projections of the signal lines on the flexible base.

公开(公告)号：US11631362B2

公开(公告)日：2023-04-18

申请号：US17535127

申请日：2021-11-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shuilang Dong ,  Shanshan Xu ,  Guangcai Yuan ,  Zhanfeng Cao ,  Ce Ning ,  Lizhong Wang ,  Dapeng Xue ,  Nianqi Yao

IPC: G09G3/3266 ,  G09G3/20 ,  G11C19/28

Abstract: A shift register unit includes an input sub-circuit, a pull-down node driving sub-circuit and an output sub-circuit. The pull-down node driving sub-circuit includes a first connection unit, a first voltage-reduction unit and a second connection unit, and configured to: under the control of the first voltage signal terminal and the pull-up node, transmit a first voltage signal from the first voltage signal terminal to the first pull-down node via the first connection unit, and reduce a voltage applied to the second connection unit via the first voltage-reduction unit; and transmit a second voltage signal from the second voltage signal terminal to the first pull-down node via the second connection unit under the control of the pull-up node.

公开(公告)号：US11239263B2

公开(公告)日：2022-02-01

申请号：US16074283

申请日：2018-01-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tianmin Zhou ,  Wei Yang ,  Lizhong Wang ,  Xiaming Zhu ,  Jipeng Song

IPC: H01L27/12 ,  H01L29/786 ,  H01L33/44

Abstract: A thin film transistor, a method for manufacturing the same and a display device are disclosed. The thin film transistor includes source-drain electrodes and a passivation layer; an isolation layer is disposed between the source-drain electrodes and the passivation layer, and the isolation layer overlays the source-drain electrodes.

公开(公告)号：US12235554B2

公开(公告)日：2025-02-25

申请号：US18026489

申请日：2022-06-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Dongfang Wang ,  Hui Guo

IPC: G02F1/1362 ,  G02F1/1368

Abstract: A display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.

公开(公告)号：US12222607B2

公开(公告)日：2025-02-11

申请号：US18024004

申请日：2022-05-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yong Yu ,  Shi Shu ,  Chuanxiang Xu ,  Yang Yue ,  Xiang Li ,  Shaohui Li ,  Ce Ning ,  Jinchao Zhang ,  Qi Yao ,  Lizhong Wang

IPC: G02F1/1339 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

Abstract: The disclosure provides a liquid crystal display panel and a display apparatus. The liquid crystal display panel of the disclosure includes: first and second substrates assembled to form a cell, a plurality of main spacers therebetween, and an auxiliary spacer around at least a portion of the main spacers. Height of the auxiliary spacer is greater than or equal to that of the main spacer. The display panel further includes: pillows on side of the first substrate close to the second substrate and each abutting against a corresponding main spacer. An orthographic projection of the main spacer on the first substrate falls within an orthographic projection of the pillow on the first substrate, and an orthographic projection of the auxiliary spacer on the first substrate does not overlap with the orthographic projection of the pillow on the first substrate.

公开(公告)号：US12191400B2

公开(公告)日：2025-01-07

申请号：US18322981

申请日：2023-05-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong Wang ,  Tianmin Zhou ,  Hehe Hu ,  Xiaochun Xu ,  Nianqi Yao ,  Dapeng Xue ,  Shuilang Dong

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

Abstract: An oxide thin film transistor includes: a gate electrode, a metal oxide active layer and a source-drain metal layer, which are on a base substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; an electron transfer rate of the carrier transport layer is greater than an electron transfer rate of the carrier isolation layer. The first metal oxide layer includes a primary surface facing toward the base substrate and a primary surface away from the base substrate; the first metal oxide layer further includes a lateral surface around the primary surfaces; the second metal oxide layer covers the lateral surface of the first metal oxide layer.

公开(公告)号：US12041795B2

公开(公告)日：2024-07-16

申请号：US17427556

申请日：2020-12-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong Wang ,  Tianmin Zhou ,  Yupeng Gao ,  Ning Dang

IPC: H10K10/46 ,  H01L29/66 ,  H01L29/786 ,  H10K59/12 ,  H10K59/125 ,  H10K77/10

CPC classification number: H10K10/484 ,  H10K59/125

Abstract: A thin film transistor, a method for manufacturing the same and a display device are disclosed, the thin film transistor includes: a first electrode, a second electrode, an active layer and a flexible conductive layer located on a substrate, one of the first electrode and the second electrode is a source, and the other thereof is a drain; the active layer is electrically coupled with the first electrode, and an orthographic projection of the active layer on the substrate is within an orthographic projection of the first electrode on the substrate; the flexible conductive layer is located on a side of the active layer away from the first electrode, and electrically couples the active layer with the second electrode.

公开(公告)号：US11925064B2

公开(公告)日：2024-03-05

申请号：US17468638

申请日：2021-09-07

Applicant: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dapeng Xue ,  Guangcai Yuan ,  Xiaochun Xu ,  Zheng Liu ,  Liangliang Li ,  Shuilang Dong ,  Lizhong Wang ,  Niangi Yao

IPC: H01L21/02 ,  H01L27/32 ,  H10K59/121 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10K59/1201

Abstract: The present disclosure provides a display substrate including: a base substrate, and a thin film transistor, an oxygen supplementing functional layer and an oxygen containing layer formed on the base substrate. The thin film transistor includes: an active layer in direct contact with the oxygen containing layer, and the active layer includes an oxide semiconductor material. The oxygen supplementing functional layer includes a metal oxide material and serves as a first electrode of the display substrate. The oxygen containing layer is between the oxygen supplementing functional layer and the base substrate.

公开(公告)号：US11798959B2

公开(公告)日：2023-10-24

申请号：US16965495

申请日：2019-07-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Guangcai Yuan ,  Ce Ning ,  Xinhong Lu ,  Tianmin Zhou ,  Lizhong Wang

IPC: H01L27/00 ,  H01L27/12

CPC classification number: H01L27/1288 ,  H01L27/1248

Abstract: Provided are an array substrate and a manufacturing method thereof, the manufacturing method includes: forming a first active layer on a base substrate; forming a second active layer; forming a second gate on the second active layer; forming a first insulating layer covering the first active layer on the second gate; patterning the first insulating layer to form first via holes at both sides of the second gate to expose the second active layer; depositing a first metal layer in the first via holes and on the first insulating layer; patterning the first metal layer, removing a part of the first metal layer above the first active layer to expose the first insulating layer; etching the first insulating layer using the patterned first metal layer as a mask, forming second via holes above the first active layer to expose the first active layer; cleaning the exposed first active layer.