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公开(公告)号：US12032014B2
公开(公告)日：2024-07-09
申请号：US16996458
申请日：2020-08-18
Inventor： Edward John Coyne , John P. Meskell , Colm Patrick Heffernan , Mark Forde , Shane Geary
IPC: G01R31/26 , H01L27/07 , H01L29/10 , H01L29/735 , H01L29/78
CPC classification number: G01R31/2608 , H01L27/0722 , H01L29/1095 , H01L29/735 , H01L29/7816
Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.
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公开(公告)号：US11988708B2
公开(公告)日：2024-05-21
申请号：US18318506
申请日：2023-05-16
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
CPC classification number: G01R31/2879 , G01N27/041 , G01R31/2874
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US20240159804A1
公开(公告)日：2024-05-16
申请号：US18419415
申请日：2024-01-22
Inventor： David J. Clarke , Stephen Denis Heffernan , Nijun Wei , Alan J. O'Donnell , Patrick Martin McGuinness , Shaun Bradley , Edward John Coyne , David Aherne , David M. Boland
IPC: G01R19/165 , G01R31/00 , G01R31/28 , H01L23/525 , H01L23/60 , H01L23/62 , H01L27/02 , H02H9/00 , H02H9/04
CPC classification number: G01R19/16504 , G01R31/002 , G01R31/2832 , G01R31/2856 , H01L23/5256 , H01L23/60 , H01L23/62 , H01L27/0288 , H02H9/00 , H02H9/042
Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically are in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes;
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Patent Agency Ranking
公开(公告)号：US20240088229A1
公开(公告)日：2024-03-14
申请号：US18510238
申请日：2023-11-15
Inventor： Edward John Coyne
IPC: H01L29/10 , H01L29/06 , H01L29/66 , H01L29/808
CPC classification number: H01L29/1083 , H01L29/0607 , H01L29/0653 , H01L29/0688 , H01L29/1066 , H01L29/66901 , H01L29/808
Abstract: A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased p-n junction was not observed. The JFET includes a lightly doped top gate and doped regions beneath the drain of the JFET.
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25.发明授权公开(公告)号：US11563084B2
公开(公告)日：2023-01-24
申请号：US16590106
申请日：2019-10-01
Inventor： Edward John Coyne , Alan Brannick , Shane Tooher , Breandán Pol Og Ó hAnnaidh , Catriona Marie O'Sullivan , Shane Patrick Geary
IPC: H01L29/08 , H01L21/8228 , H01L27/082 , H01L29/66 , H01L29/732
Abstract: A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.
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公开(公告)号：US20220252664A1
公开(公告)日：2022-08-11
申请号：US17652857
申请日：2022-02-28
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US11269006B2
公开(公告)日：2022-03-08
申请号：US17062225
申请日：2020-10-02
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US20210098575A1
公开(公告)日：2021-04-01
申请号：US16590142
申请日：2019-10-01
Inventor： Edward John Coyne , Alan Brannick , Shane Tooher , Breandán Pol Og Ó hAnnaidh , Catriona Marie O'Sullivan , Shane Patrick Geary
IPC: H01L29/08 , H01L29/66 , H01L29/732 , H01L29/40 , H01L27/082 , H01L21/8228
Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.
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