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    TIMER FOR USE DUAL VOLTAGE SUPPLIES
    24.
    发明申请
    TIMER FOR USE DUAL VOLTAGE SUPPLIES 审中-公开

    公开(公告)号：US20200312389A1

    公开(公告)日：2020-10-01

    申请号：US16370579

    申请日：2019-03-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Srinivas R. Sathu ,  John Wuu ,  Russell Schreiber ,  Martin Piorkowski

    IPC: G11C7/22 ,  G11C11/419

    Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.

    Memory with expandable row width
    25.
    发明授权
    Memory with expandable row width 有权

    公开(公告)号：US10783953B2

    公开(公告)日：2020-09-22

    申请号：US15830176

    申请日：2017-12-04

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Wuu ,  Martin Paul Piorkowski

    IPC: G11C7/12 ,  G11C11/419 ,  G11C11/418

    Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

    FLEXIBILE INTERFACES USING THROUGH-SILICON VIA TECHNOLOGY
    27.
    发明申请
    FLEXIBILE INTERFACES USING THROUGH-SILICON VIA TECHNOLOGY 审中-公开

    公开(公告)号：US20190268086A1

    公开(公告)日：2019-08-29

    申请号：US15903253

    申请日：2018-02-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Wuu ,  Samuel Naffziger ,  Michael K. Ciraula ,  Russell Schreiber

    IPC: H04J99/00 ,  H01L23/48 ,  H01L23/00

    Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

    Voltage-aware signal path synchronization
    28.
    发明授权
    Voltage-aware signal path synchronization 有权
    电压感知信号路径同步

    公开(公告)号：US09053257B2

    公开(公告)日：2015-06-09

    申请号：US13668705

    申请日：2012-11-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber ,  John Wuu ,  Keith Kasprak

    IPC: H03K19/00 ,  G06F17/50 ,  G06F13/16 ,  H05K3/00 ,  G06F13/42

    CPC classification number: G06F17/50 ,  G06F13/1689 ,  G06F13/4291 ,  G06F17/5045 ,  G06F2217/62 ,  H03K19/00 ,  H05K3/00

    Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

    Abstract translation: 集成电路（IC）根据其工作电压电平产生时钟延迟控制信号。 时钟延迟控制信号被路由到对应的时钟门控逻辑，其控制相应信号路径的输出的同步捕获。 响应于对应的接收时钟延迟控制的断言，时钟门控逻辑延迟由相应触发器使用的时钟信号。 因此，用于捕获某些信号路径的输出的时钟信号可能在某些电压条件下被延迟。 即使在不同的工作电压条件下不同的信号路径可能表现出不同的相对路径延迟，不同信号路径的这种选择性时钟路径延迟使得IC能够使用更高的时钟频率，或者更可靠地锁定一定时钟频率的路径输出。

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