知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.018 seconds)

    CHIP-ON-WAFER FACE-TO-BACK HYBRID BONDING WITHOUT SUPPORT CARRIER
    4.
    发明申请
    CHIP-ON-WAFER FACE-TO-BACK HYBRID BONDING WITHOUT SUPPORT CARRIER 有权

    公开(公告)号：US20250112047A1

    公开(公告)日：2025-04-03

    申请号：US18478746

    申请日：2023-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Chandra Sekhar Mandalapu ,  Raja Swaminathan ,  Liwei Wang ,  John Wuu

    IPC: H01L21/20 ,  H01L21/683 ,  H01L23/00

    Abstract: A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.

    Semiconductor package with annular package lid structure
    6.
    发明授权
    Semiconductor package with annular package lid structure 有权

    公开(公告)号：US12278150B2

    公开(公告)日：2025-04-15

    申请号：US17490943

    申请日：2021-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Priyal Shah ,  Brett P. Wilkerson ,  Raja Swaminathan

    IPC: H01L23/053 ,  H01L21/48 ,  H01L21/52 ,  H01L23/367 ,  H01L23/498

    Abstract: A semiconductor package includes a substrate having opposing first and second surfaces as well as a semiconductor chip component disposed at the second surface and having third and fourth opposing surfaces. A package lid structure is affixed to the second surface of the substrate and the fourth surface of the semiconductor chip component, and has a planar component overlying the semiconductor chip component and having a fifth surface facing the fourth surface and an opposing sixth surface. The planar component includes an aperture extending between the fifth surface and the sixth surface so as to expose at least a portion of the fourth surface of the semiconductor chip component. A thermal exchange structure can be mounted on the package lid structure to form a thermal extraction pathway with the semiconductor die component via the aperture, either directly or via an interposing thermally conductive plate.

    3D semiconductor package with die-mounted voltage regulator
    8.
    发明授权
    3D semiconductor package with die-mounted voltage regulator 有权

    公开(公告)号：US12165981B2

    公开(公告)日：2024-12-10

    申请号：US17556346

    申请日：2021-12-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H Loh ,  Raja Swaminathan ,  Rahul Agarwal ,  Brett P. Wilkerson

    IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

    Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

    Fanout module integrating a photonic integrated circuit
    10.
    发明授权
    Fanout module integrating a photonic integrated circuit 有权

    公开(公告)号：US12276850B2

    公开(公告)日：2025-04-15

    申请号：US18357376

    申请日：2023-07-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

    IPC: G02B6/42 ,  G02B6/43

    Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

Patent Agency Ranking