公开(公告)号：US12249519B2

公开(公告)日：2025-03-11

申请号：US17843938

申请日：2022-06-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US12183675B2

公开(公告)日：2024-12-31

申请号：US16351728

申请日：2019-03-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Chia-Hao Cheng ,  Milind S. Bhagavat

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

公开(公告)号：US20240063206A1

公开(公告)日：2024-02-22

申请号：US18497961

申请日：2023-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind Bhagavat ,  Brett Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08146

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

公开(公告)号：US11749629B2

公开(公告)日：2023-09-05

申请号：US17118126

申请日：2020-12-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/81 ,  H01L2224/02331

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

公开(公告)号：US11670624B2

公开(公告)日：2023-06-06

申请号：US17120753

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49827 ,  H01L28/40

Abstract: An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.

公开(公告)号：US11658123B2

公开(公告)日：2023-05-23

申请号：US17032544

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L24/13 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2224/24991 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/25177 ,  H01L2224/82801

Abstract: A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).

公开(公告)号：US10930621B2

公开(公告)日：2021-02-23

申请号：US16930761

申请日：2020-07-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

公开(公告)号：US10825692B2

公开(公告)日：2020-11-03

申请号：US16226790

申请日：2018-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Ivor Barber ,  Venkatachalam Valliappan ,  Yuen Ting Cheng ,  Guan Sin Chok

IPC: H01L21/322 ,  H01L29/34 ,  H01L21/268

Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.

公开(公告)号：US12276850B2

公开(公告)日：2025-04-15

申请号：US18357376

申请日：2023-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

IPC: G02B6/42 ,  G02B6/43

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US12107075B2

公开(公告)日：2024-10-01

申请号：US18324744

申请日：2023-05-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lei Fu ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5381 ,  H01L23/5389 ,  H01L24/13 ,  H01L2225/06541

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.