公开(公告)号：US20200312389A1

公开(公告)日：2020-10-01

申请号：US16370579

申请日：2019-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Srinivas R. Sathu ,  John Wuu ,  Russell Schreiber ,  Martin Piorkowski

IPC: G11C7/22 ,  G11C11/419

Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.