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公开(公告)号：US12153222B2
公开(公告)日：2024-11-26
申请号：US18360193
申请日：2023-07-27
Inventor： Rajesh Katkar , Belgacem Haba
IPC: G02B27/01 , G02B27/10 , G02B27/14 , H01L25/075
Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.
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公开(公告)号：US20240387439A1
公开(公告)日：2024-11-21
申请号：US18784724
申请日：2024-07-25
Inventor： Belgacem Haba , Laura Wills Mirkarimi , Javier A. DeLaCruz , Rajesh Katkar , Cyprian Emeka Uzoh , Guilian Gao , Thomas Workman
Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
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23.发明申请公开(公告)号：US20240387323A1
公开(公告)日：2024-11-21
申请号：US18512547
申请日：2023-11-17
Inventor： Belgacem Haba , Rajesh Katkar
IPC: H01L23/473 , H01L23/00 , H01L23/427 , H01L23/498 , H01L25/18 , H10B80/00
Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.
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公开(公告)号：US20240312951A1
公开(公告)日：2024-09-19
申请号：US18183768
申请日：2023-03-14
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Gaius Gillman Fountain, JR. , Belgacem Haba , Rajesh Katkar
IPC: H01L23/00 , H01L21/027 , H01L21/56 , H01L23/12 , H01L25/16
CPC classification number: H01L24/80 , H01L21/0273 , H01L21/561 , H01L23/12 , H01L24/03 , H01L24/08 , H01L24/96 , H01L25/162 , H01L25/167 , H01L2224/0345 , H01L2224/03452 , H01L2224/03831 , H01L2224/03845 , H01L2224/08145 , H01L2224/80011 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/96 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043
Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.
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公开(公告)号：US12046571B2
公开(公告)日：2024-07-23
申请号：US18058693
申请日：2022-11-23
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Liang Wang , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/26 , H01L24/03 , H01L24/09 , H01L24/27 , H01L24/30 , H01L24/83 , H01L2224/08257 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028
Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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Patent Agency Ranking
26.发明公开公开(公告)号：US20240203948A1
公开(公告)日：2024-06-20
申请号：US18589231
申请日：2024-02-27
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Belgacem Haba , Gabriel Z. Guevara , Joy Watanabe
IPC: H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L21/561 , H01L23/3121 , H01L24/97 , H01L2224/0401 , H01L2924/3511 , H01L2924/35121
Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
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27.发明授权公开(公告)号：US11967575B2
公开(公告)日：2024-04-23
申请号：US17681019
申请日：2022-02-25
Inventor： Guilian Gao , Javier A. DeLaCruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, Jr. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L24/06 , H01L24/74 , H01L24/80 , H01L24/89 , H01L2224/05557 , H01L2224/06131 , H01L2224/06177 , H01L2224/08147 , H01L2224/80007 , H01L2224/80011 , H01L2224/80031 , H01L2224/80047 , H01L2224/8013 , H01L2224/80895 , H01L2224/80896 , H01L2924/3512
Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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公开(公告)号：US20240096823A1
公开(公告)日：2024-03-21
申请号：US18520337
申请日：2023-11-27
Inventor： Javier A. DeLaCruz , Belgacem Haba , Rajesh Katkar
IPC: H01L23/00 , H01L21/66 , H01L23/528
CPC classification number: H01L23/573 , H01L22/34 , H01L23/528 , H01L23/562 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/49 , H01L2224/08237 , H01L2224/29082 , H01L2224/29187 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48225 , H01L2224/49171 , H01L2224/73215
Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
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公开(公告)号：US20230420399A1
公开(公告)日：2023-12-28
申请号：US18462691
申请日：2023-09-07
Inventor： Belgacem Haba , Rajesh Katkar , Ilyas Mohammed , Javier A. DeLaCruz
CPC classification number: H01L24/08 , H01L24/80 , H01L24/94 , H01L21/78 , H01L2224/80896 , H01L2224/08146 , H01L2224/80006 , H01L2224/80895
Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
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公开(公告)号：US20230420313A1
公开(公告)日：2023-12-28
申请号：US18463080
申请日：2023-09-07
Inventor： Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh , Shaowu Huang , Guilian Gao , Ilyas Mohammed
CPC classification number: H01L23/10 , B81C1/00333 , B81B7/0074 , B81B7/0032 , B81C1/00261 , H01L23/04 , H01L23/053 , H01L23/02 , B81C1/00269 , B81C2203/038
Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
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