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公开(公告)号：US07564729B2
公开(公告)日：2009-07-21
申请号：US12057011
申请日：2008-03-27
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。
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公开(公告)号：US07290203B2
公开(公告)日：2007-10-30
申请号：US10977432
申请日：2004-10-29
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括错误编码电路，其操作以接收输入数据字并产生存储在动态存储器中的编码数据字。 该装置还包括一个解码电路，用于从动态存储器接收编码的数据字，以检测从动态存储器读取的输入数据字中的至少一个或多个单向错误，并且当至少一个错误 检测出指示输入数据字包含过期数据的错误信号。 包括在装置中的控制电路被配置为响应于该误差信号启动一个或多个动作。
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23.发明授权公开(公告)号：US06269040B1
公开(公告)日：2001-07-31
申请号：US09603632
申请日：2000-06-26
IPC分类号： G11C702
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1051 , G11C7/18
摘要： An interconnection network for connecting memory cells to sense amplifiers in a memory device includes a plurality of sub-arrays having memory cells, a plurality of switch units each of which is associated with a corresponding one of the plurality of sub-arrays, and true and complement input lines of the sense amplifiers each of which receives data from a selected memory cell via an input line and reference from reference cells via the other input line. The reference, which is a mid-level of data in the memory cells, is obtained from a reference cell having the mid-level value. Alternatively, a mid-level reference may be obtained by averaging data of logic values “1” and “0” stored in different reference cells. The reference cells may be disposed in the sub-arrays or outside the sub-arrays. The interconnection network of the present invention has symmetric configuration so that networks of the input lines of the sense amplifiers have substantially equal structure. Both inputs of a sense amplifier have substantially equal number of connections to data columns and reference columns.
摘要翻译： 用于将存储器单元连接到存储器件中的感测放大器的互连网络包括具有存储器单元的多个子阵列，多个开关单元，每个开关单元与多个子阵列中的相应一个子阵列相关联， 读出放大器的补码输入线，每个读出放大器经由输入线从参考单元经由输入线接收数据，并经由另一输入线从参考单元接收数据。 作为存储器单元中的数据中间值的参考是从具有中间值的参考单元获得的。 或者，可以通过平均存储在不同参考单元中的逻辑值“1”和“0”的数据来获得中间级参考。 参考单元可以设置在子阵列中或子阵列外部。 本发明的互连网络具有对称配置，使得感测放大器的输入线的网络具有基本相同的结构。 读出放大器的两个输入端具有与数据列和参考列基本上相等数量的连接。
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24.发明申请公开(公告)号：US20090198970A1
公开(公告)日：2009-08-06
申请号：US12023495
申请日：2008-01-31
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3869 , G06F9/3873
摘要： An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.
摘要翻译： 电子装置包括多个级串联地连接作为流水线，以对输入操作数进行顺序处理。 与流水线的至少一个级相关联的缩短电路识别出当适当的时候，对于阶段的输入操作数中的一个或多个已被预先确定，以便缩短并执行缩短。
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公开(公告)号：US20090019341A1
公开(公告)日：2009-01-15
申请号：US11776810
申请日：2007-07-12
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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公开(公告)号：US06975555B2
公开(公告)日：2005-12-13
申请号：US10976598
申请日：2004-10-29
CPC分类号： G11C11/16
摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.
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27.发明授权公开(公告)号：US06894916B2
公开(公告)日：2005-05-17
申请号：US10256715
申请日：2002-09-27
申请人： William Robert Reohr , Li-Kong Wang
发明人： William Robert Reohr , Li-Kong Wang
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , G11C5/06
CPC分类号： G11C11/22
摘要： An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.
摘要翻译： 改进的非易失性存储器阵列包括多个存储器单元，至少一个存储器单元包括用于存储至少一个存储器单元的逻辑状态的三端非易失性存储元件。 存储器阵列还包括可操作地耦合到存储器单元的多个写入线，用于选择性地将存储器阵列中的一个或多个存储器单元的逻辑状态写入，并且可操作地耦合到存储器单元的多个位线和字线用于选择性地 读取和写入存储器阵列中的一个或多个存储器单元的逻辑状态。 有利地，存储器阵列被配置为消除对可操作地耦合到至少一个存储器单元中的对应的非易失性存储元件的通过栅极的需要。
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公开(公告)号：US06778429B1
公开(公告)日：2004-08-17
申请号：US10452418
申请日：2003-06-02
申请人： Yu Lu , William Robert Reohr
发明人： Yu Lu , William Robert Reohr
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A write circuit for selectively writing one or more magnetic memory cells in an MRAM includes at least one programmable current source being couplable to one or more global word lines in the MRAM, the programmable current source including an input for receiving a first control signal and an output, the programmable current source generating at least a portion of a write current at the output having a magnitude which varies in response to the first control signal. The write circuit further includes a plurality of current sinks, each current sink being couplable to one or more global word lines in the MRAM, each current sink including an input for receiving a second control signal, each current sink returning at least a portion of the write current in response to the second control signal. A controller operatively coupled to the at least one programmable current source and the plurality of current sinks is operative to generate the first and second control signals and to selectively distribute the write current across a plurality of global word lines in the MRAM so that stray magnetic field interaction between selected memory cells and half-selected and/or unselected memory cells in the MRAM is minimized.
摘要翻译： 用于选择性地写入MRAM中的一个或多个磁存储器单元的写入电路包括至少一个可耦合到MRAM中的一个或多个全局字线的可编程电流源，可编程电流源包括用于接收第一控制信号和 输出，所述可编程电流源在所述输出处产生具有响应于所述第一控制信号而变化的幅度的写入电流的至少一部分。 写入电路还包括多个电流吸收器，每个电流吸收器可耦合到MRAM中的一个或多个全局字线，每个电流吸收器包括用于接收第二控制信号的输入端，每个电流吸收器返回至少一部分 响应于第二控制信号写入电流。 可操作地耦合到所述至少一个可编程电流源和所述多个电流吸收器的控制器可操作以产生所述第一和第二控制信号，并且选择性地分配所述MRAM中的多个全局字线上的写入电流，使得杂散磁场 选择的存储器单元和MRAM中的半选择和/或未选择的存储器单元之间的交互被最小化。
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公开(公告)号：US06389505B1
公开(公告)日：2002-05-14
申请号：US09196086
申请日：1998-11-19
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F12/0802
摘要： A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.
摘要翻译： 一种用于通过仅恢复在分配的数据保留时间内未被读取或写入的那些单元来减少维持DRAM中的数据所需的刷新动作数量的系统和方法。 一个实施例描述了应用于DRAM高速缓存的还原跟踪系统。 还原跟踪系统可以替代地应用于具有信息重复的任何存储器架构。 例如，可以通过记录和更新DRAM中的一个或多个数据条目的刷新状态来减少维护DRAM中的数据条目所需的刷新动作的数量; 并使那些具有过期状态的数据条目无效。 因此，可以使更多的存储器带宽可用于计算机系统。
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30.发明授权Segmented write line architecture for writing magnetic random access memories 有权用于写入磁随机存取存储器的分段写行架构公开(公告)号：US06335890B1
公开(公告)日：2002-01-01
申请号：US09703963
申请日：2000-11-01
IPC分类号： G11C1102
摘要： An architecture for selectively writing one or more magnetic memory cells in a magnetic random access memory (MRAM) device comprises at least one write line including a global write line conductor and a plurality of segmented write line conductors connected thereto, the global write line conductor being substantially isolated from the memory cells. The architecture further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line conductor, and a plurality of segmented group select switches, each group select switch being operatively connected between a corresponding segmented write line conductor and a write line current return conductor, the group select switch including a group select input for receiving a group select signal, the group select switch substantially completing an electrical circuit between the corresponding segmented write line conductor and the write line current return conductor in response to the group select signal. A plurality of bit lines are operatively coupled to the magnetic memory cells for selectively writing the state of the memory cells.
摘要翻译： 一种用于在磁随机存取存储器（MRAM）装置中选择性地写入一个或多个磁存储单元的架构包括至少一条写入线，包括全局写线导体和连接到其上的多个分段写线导体，全局写线导体为 基本上与记忆细胞分离。 该架构还包括多个分段组，每个分段组包括可操作地耦合到对应的分段写线路导体的多个存储单元，以及多个分组组选择开关，每个组选择开关可操作地连接在相应的分段写入 线路导体和写入线路电流返回导体，组选择开关包括用于接收组选择信号的组选择输入，组选择开关基本上完成对应的分段写入线导体和写入线电流返回导体之间的电路 响应组选择信号。 多个位线可操作地耦合到磁存储器单元，用于选择性地写入存储单元的状态。
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