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公开(公告)号：US06975555B2
公开(公告)日：2005-12-13
申请号：US10976598
申请日：2004-10-29
CPC分类号： G11C11/16
摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.
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公开(公告)号：US06778429B1
公开(公告)日：2004-08-17
申请号：US10452418
申请日：2003-06-02
申请人： Yu Lu , William Robert Reohr
发明人： Yu Lu , William Robert Reohr
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A write circuit for selectively writing one or more magnetic memory cells in an MRAM includes at least one programmable current source being couplable to one or more global word lines in the MRAM, the programmable current source including an input for receiving a first control signal and an output, the programmable current source generating at least a portion of a write current at the output having a magnitude which varies in response to the first control signal. The write circuit further includes a plurality of current sinks, each current sink being couplable to one or more global word lines in the MRAM, each current sink including an input for receiving a second control signal, each current sink returning at least a portion of the write current in response to the second control signal. A controller operatively coupled to the at least one programmable current source and the plurality of current sinks is operative to generate the first and second control signals and to selectively distribute the write current across a plurality of global word lines in the MRAM so that stray magnetic field interaction between selected memory cells and half-selected and/or unselected memory cells in the MRAM is minimized.
摘要翻译： 用于选择性地写入MRAM中的一个或多个磁存储器单元的写入电路包括至少一个可耦合到MRAM中的一个或多个全局字线的可编程电流源，可编程电流源包括用于接收第一控制信号和 输出，所述可编程电流源在所述输出处产生具有响应于所述第一控制信号而变化的幅度的写入电流的至少一部分。 写入电路还包括多个电流吸收器，每个电流吸收器可耦合到MRAM中的一个或多个全局字线，每个电流吸收器包括用于接收第二控制信号的输入端，每个电流吸收器返回至少一部分 响应于第二控制信号写入电流。 可操作地耦合到所述至少一个可编程电流源和所述多个电流吸收器的控制器可操作以产生所述第一和第二控制信号，并且选择性地分配所述MRAM中的多个全局字线上的写入电流，使得杂散磁场 选择的存储器单元和MRAM中的半选择和/或未选择的存储器单元之间的交互被最小化。
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3.发明授权Magnetic random access memory using memory cells with rotated magnetic storage elements 有权使用具有旋转磁存储元件的存储单元的磁性随机存取存储器公开(公告)号：US06816431B1
公开(公告)日：2004-11-09
申请号：US10446297
申请日：2003-05-28
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.
摘要翻译： 磁性随机存取存储器电路包括多个磁存储器单元，每个存储单元包括具有容易轴的磁存储元件和与其相关联的硬轴，以及多个列线和行线，用于选择性地访问一个或多个 的存储单元，每个存储器单元靠近一列列线和一行行的交点。 每个磁存储单元被布置成使得容易轴基本上平行于感测电流的流动方向，并且硬轴基本上平行于写入电流的流动方向。
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4.发明授权Segmented word line architecture for cross point magnetic random access memory 有权用于交叉磁性随机存取存储器的分段字线架构公开(公告)号：US06816405B1
公开(公告)日：2004-11-09
申请号：US10452177
申请日：2003-06-02
申请人： Yu Lu , William Robert Reohr
发明人： Yu Lu , William Robert Reohr
IPC分类号： G11C1114
CPC分类号： G11C11/16
摘要： An MRAM comprises a plurality of magnetic memory cells, a plurality of local word lines, each of the local word lines being operatively coupled to at least one memory cell for assisting in writing a logical state of the at least one memory cell corresponding thereto, a plurality of global word lines, each of the plurality of global word lines being connected to at least one of the plurality of local word lines, the global word lines being substantially isolated from the memory cells, a plurality of write circuits operatively coupled to the global word lines, and a plurality bit lines operatively coupled to the memory cells for selectively writing a logical state of one or more of the memory cells. Each of the write circuits is configurable as a current source and/or a current sink for supplying and/or returning, respectively, at least a portion of a write current for assisting in writing one or more memory cells. The write circuits are configured to selectively distribute the write current across at least a plurality of global word lines so that stray magnetic field interaction between selected memory cells and half-selected and/or unselected memory cells is reduced.
摘要翻译： MRAM包括多个磁存储器单元，多个本地字线，每个本地字线可操作地耦合到至少一个存储单元，用于辅助写入与之对应的至少一个存储单元的逻辑状态， 多个全局字线，多个全局字线中的每一个连接到多个本地字线中的至少一个，全局字线基本上与存储器单元隔离;多个写入电路，可操作地耦合到全局字线 字线和可操作地耦合到存储器单元的多个位线，用于选择性地写入一个或多个存储器单元的逻辑状态。 写入电路中的每一个可配置为电流源和/或电流吸收器，用于分别提供和/或返回至少一部分写入电流，用于辅助写入一个或多个存储器单元。 写入电路被配置为选择性地分布至少多个全局字线的写入电流，使得选择的存储器单元与半选择和/或未选择的存储单元之间的杂散磁场相互作用减小。
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公开(公告)号：US08860425B2
公开(公告)日：2014-10-14
申请号：US13411068
申请日：2012-03-02
IPC分类号： G01R31/14
CPC分类号： G01R31/3008
摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.
摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。
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公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
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公开(公告)号：US20110199837A1
公开(公告)日：2011-08-18
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
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8.发明授权公开(公告)号：US07945765B2
公开(公告)日：2011-05-17
申请号：US12023495
申请日：2008-01-31
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3869 , G06F9/3873
摘要： An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.
摘要翻译： 电子装置包括多个级串联地连接作为流水线，以对输入操作数进行顺序处理。 与流水线的至少一个级相关联的缩短电路识别出当适当的时候，对于阶段的输入操作数中的一个或多个已被预先确定，以便缩短并执行缩短。
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公开(公告)号：US07920434B2
公开(公告)日：2011-04-05
申请号：US12199438
申请日：2008-08-27
IPC分类号： G11C5/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.
摘要翻译： 提供了用于感测存储器阵列中的相应存储器单元的数据状态的技术，所述存储器阵列至少包括耦合到所述存储器单元的至少一个子集的第一位线。 在一个方面，用于感测存储器阵列中各个存储单元的数据状态的电路包括耦合到第一位线的至少一个读出放大器。 感测放大器包括第一晶体管，其操作以选择性地禁止第一位线的充电，其方式与在与读出放大器耦合的第二位线上的电压电平无关。
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公开(公告)号：US07564729B2
公开(公告)日：2009-07-21
申请号：US12057011
申请日：2008-03-27
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。
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