公开(公告)号：US20120139009A1

公开(公告)日：2012-06-07

申请号：US12958647

申请日：2010-12-02

申请人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

发明人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

IPC分类号： H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/7317 ,  H01L27/0821 ,  H01L27/1203 ,  H01L29/0808 ,  H01L29/165 ,  H01L29/66265

摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。 因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。 基底还可以包括上硅基区和/或下硅基区。 在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。 此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

公开(公告)号：US07947589B2

公开(公告)日：2011-05-24

申请号：US12552774

申请日：2009-09-02

申请人： Ramachandran Muralidhar ,  Marwan H. Khater

发明人： Ramachandran Muralidhar ,  Marwan H. Khater

IPC分类号： H01L21/3205

CPC分类号： H01L29/66795 ,  H01L21/3086 ,  H01L21/845

摘要： A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

摘要翻译： 半导体工艺和装置通过形成通过掩埋绝缘体层（18）与下层第一单晶半导体层（17）隔离的第二单晶半导体层（19）来提供FinFET器件; 图案化和蚀刻第二单晶半导体层（19）以形成具有垂直侧壁的单晶心轴（42）; 热氧化单晶心轴的垂直侧壁以生长具有基本均匀厚度的氧化物间隔物（52）; 选择性地去除所述单晶心轴（42）的任何剩余部分，同时基本上保持所述氧化物间隔物（52）; 以及使用所述氧化物间隔物（52）选择性地蚀刻所述第一单晶半导体层（17）以形成一个或多个FinFET沟道区域（92）。

公开(公告)号：US07732292B2

公开(公告)日：2010-06-08

申请号：US11838948

申请日：2007-08-15

申请人： Marwan H. Khater ,  Francois Pagette

发明人： Marwan H. Khater ,  Francois Pagette

IPC分类号： H01L21/331

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/732

摘要： Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.

摘要翻译： 公开了一种在集成电路结构中形成晶体管的方法，其通过在基板中形成集电体和在集电极之上形成本征基极而开始。 然后，本发明在基底上方的发光体的下部的内部基底上形成发射极基座。 在实际形成发射极或者相关的间隔物之前，本发明在不受发射极基座保护的衬底的区域中形成非本征基极。 之后，本发明去除发射器基座并最终形成发射器底座所在的发射极。

公开(公告)号：US07611954B2

公开(公告)日：2009-11-03

申请号：US11150894

申请日：2005-06-13

申请人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette

发明人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette

IPC分类号： H01L21/8222

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/732

摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.

摘要翻译： 公开了具有包括外部区域和不同掺杂浓度的内部区域的升高的外部基极的自对准双极晶体管结构和制造晶体管的方法。 更具体地说，外部碱基与发射体的自对准是通过在两个区域中形成外部碱基来实现的。 首先，提供具有第一掺杂浓度的硅或多晶硅的第一材料以形成外部外在基极区域。 然后通过光刻形成在第一材料层中的第一开口，在该第一材料层内形成有虚拟发射极基座，这导致在第一开口的侧壁和虚拟基座之间形成沟槽。 然后在沟槽的内部提供第二掺杂浓度的第二材料，形成不同的内部非本征基本延伸区域，以将凸起的本征基底边缘自对准到虚拟基座边缘。 由于发射极形成在存在虚拟基座的位置，所以外部基极也与发射极自对准。 形成内部非本征基极延伸区域的硅或多晶硅也可以在具有选择性或非选择性外延的沟槽中生长。

公开(公告)号：US07390721B2

公开(公告)日：2008-06-24

申请号：US11231385

申请日：2005-09-21

申请人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

发明人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US07341920B2

公开(公告)日：2008-03-11

申请号：US11160706

申请日：2005-07-06

申请人： Marwan H. Khater

发明人： Marwan H. Khater

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L27/082

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242

摘要： Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

摘要翻译： 公开了制造具有自对准凸起外部基极的双极晶体管的方法的实施例。 在该方法中，在具有能够使用当前最先进的光刻图案化的最小尺寸的基板上形成介电垫。 开口在电介质垫的上方对准，并通过隔离氧化层蚀刻到外在的基层。 开口的尺寸等于或大于电介质垫。 通过外部基极层蚀刻另一个较小的开口到电介质垫。 使用多步蚀刻工艺来从介电垫的表面选择性地去除非本征基层，然后选择性地去除介电垫。 然后在所得沟槽中形成发射极。 所得到的晶体管结构在发射极的下部边缘与外部基极的边缘之间具有最小化的距离，从而降低电阻。

公开(公告)号：US07087940B2

公开(公告)日：2006-08-08

申请号：US10709220

申请日：2004-04-22

申请人： Marwan H. Khater ,  Francois Pagette

发明人： Marwan H. Khater ,  Francois Pagette

IPC分类号： H01L31/072 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7378

摘要： A bipolar transistor structure and method of making the bipolar transistor are provided. The bipolar transistor includes a collector region, an intrinsic base layer overlying the collector region, and an emitter overlying the intrinsic base layer. An opened etch stop layer includes a layer of dielectric material overlying the intrinsic base, the opened etch stop layer self-aligned to the emitter. The bipolar transistor further includes a raised extrinsic base self-aligned to the emitter, the raised extrinsic base overlying the intrinsic base layer.

摘要翻译： 提供双极晶体管结构和制造双极晶体管的方法。 双极晶体管包括集电极区域，覆盖集电极区域的本征基极层和覆盖本征基极层的发射极。 开放的蚀刻停止层包括覆盖本征基底的介电材料层，该开放的蚀刻停止层与发射极自对准。 双极晶体管还包括与发射极自对准的升高的外部基极，凸起的外在基极覆盖本征基极层。

公开(公告)号：US06960820B2

公开(公告)日：2005-11-01

申请号：US10604212

申请日：2003-07-01

申请人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette

发明人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette

IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/732

摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.

摘要翻译： 公开了具有包括外部区域和不同掺杂浓度的内部区域的升高的外部基极的自对准双极晶体管结构和制造晶体管的方法。 更具体地说，外部碱基与发射体的自对准是通过在两个区域中形成外部碱基来实现的。 首先，提供具有第一掺杂浓度的硅或多晶硅的第一材料以形成外部外在基极区域。 然后通过光刻形成在第一材料层中的第一开口，在该第一材料层内形成有虚拟发射极基座，这导致在第一开口的侧壁和虚拟基座之间形成沟槽。 然后在沟槽内部设置第二掺杂浓度的第二材料，形成不同的内部非本征基本延伸区域，以将凸起的本征基底边缘自对准到虚拟基座边缘。 由于发射极形成在存在虚拟基座的位置，所以外部基极也与发射极自对准。 形成内部非本征基极延伸区域的硅或多晶硅也可以在具有选择性或非选择性外延的沟槽中生长。

公开(公告)号：US09029132B2

公开(公告)日：2015-05-12

申请号：US12537063

申请日：2009-08-06

申请人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

发明人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

IPC分类号： C12M1/34 ,  G01N33/551 ,  G01N33/543 ,  B82Y10/00 ,  G01N27/327 ,  H01L29/78

CPC分类号： G01N33/54373 ,  B82Y10/00 ,  G01N27/3276 ,  G01N27/4145 ,  G01N33/543 ,  H01L29/785 ,  Y10S977/721 ,  Y10S977/92 ,  Y10S977/953

摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.

摘要翻译： 用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动 当生物分子与抗体结合时，在源区和漏区之间变化。

公开(公告)号：US20140030835A1

公开(公告)日：2014-01-30

申请号：US13586187

申请日：2012-08-15

申请人： Solomon Assefa ,  William M. J. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

发明人： Solomon Assefa ,  William M. J. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

IPC分类号： H01L33/02

CPC分类号： H01L27/1203

摘要： A semiconductor structure includes a photonic modulator and a field effect transistor on a same substrate. The photonic modulator includes a modulator semiconductor structure and a semiconductor contact structure employing a same semiconductor material as a gate electrode of a field effect transistor. The modulator semiconductor structure includes a lateral p-n junction, and the semiconductor contact structure includes another lateral p-n junction. To form this semiconductor structure, the modulator semiconductor structure in the shape of a waveguide and an active region of a field effect transistor region can be patterned in a semiconductor substrate. A gate dielectric layer is formed on the modulator semiconductor structure and the active region, and is subsequently removed from the modulator semiconductor structure. A semiconductor material layer is deposited, patterned, and doped with patterns to form a gate electrode for the field effect transistor and the semiconductor contact structure for the waveguide.

摘要翻译： 半导体结构包括在相同衬底上的光子调制器和场效应晶体管。 光调制器包括调制器半导体结构和使用与场效应晶体管的栅电极相同的半导体材料的半导体接触结构。 调制器半导体结构包括横向p-n结，并且半导体接触结构包括另一个侧向p-n结。 为了形成该半导体结构，可以在半导体衬底中构造波导形状的调制器半导体结构和场效应晶体管区的有源区。 栅极电介质层形成在调制器半导体结构和有源区上，随后从调制器半导体结构中去除。 沉积，图案化和掺杂半导体材料层以形成场效应晶体管的栅电极和用于波导的半导体接触结构。