公开(公告)号：US08223558B2

公开(公告)日：2012-07-17

申请号：US13179714

申请日：2011-07-11

Applicant: Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

Inventor： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Abstract translation: NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US08222953B2

公开(公告)日：2012-07-17

申请号：US13221311

申请日：2011-08-30

Applicant: Hiroshi Nakamura

Inventor： Hiroshi Nakamura

IPC: G05F1/10

CPC classification number: H02M3/073 ,  H02M2003/075 ,  H02M2003/077 ,  H02M2003/078

Abstract: A boost circuit includes: first transistors connected in series between a voltage input node and a voltage output node to constitute a charge transfer circuit; and first capacitors, one ends of which are coupled to the respective connection nodes between the first transistors, the other ends thereof being applied with clocks with plural phases, wherein a gate of a certain stage transistor corresponding to one of the first transistors in the charge transfer circuit is coupled to a drain of another stage transistor corresponding to another one of the first transistors, which is disposed nearer to the voltage output node than the certain stage transistor and driven by the same phase clock as that of the certain stage transistor, the certain stage transistor being disposed nearer to the voltage output node than an initial stage transistor.

Abstract translation: 升压电路包括：串联连接在电压输入节点和电压输出节点之间的第一晶体管，构成电荷转移电路; 以及第一电容器，其一端耦合到第一晶体管之间的相应连接节点，其另一端被施加具有多相的时钟，其中一个级晶体管的栅极对应于电荷中的第一晶体管之一 传输电路耦合到与第一晶体管中的另一个晶体管相对应的另一级晶体管的漏极，第一晶体管的布置比特定级晶体管更靠近电压输出节点并且由与某一级晶体管相同的相位时钟驱动， 特定级晶体管被设置为比初始级晶体管更靠近电压输出节点。

公开(公告)号：US08218374B2

公开(公告)日：2012-07-10

申请号：US12981163

申请日：2010-12-29

Applicant: Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/10

CPC classification number: G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US08216720B2

公开(公告)日：2012-07-10

申请号：US10519073

申请日：2003-06-25

Applicant: Atsushi Fukui ,  Yasuyuki Kusumoto ,  Mariko Torimae ,  Hiroshi Nakamura

Inventor： Atsushi Fukui ,  Yasuyuki Kusumoto ,  Mariko Torimae ,  Hiroshi Nakamura

IPC: H01M4/13 ,  H01M4/88

CPC classification number: H01M4/134 ,  H01M4/386 ,  H01M4/405 ,  H01M4/621 ,  H01M4/661 ,  H01M10/052

Abstract: A negative electrode for a lithium secondary cell having a collector composed of an electroconductive metal foil and, provided on the surface thereof, an active material layer containing active material particles containing silicon and/or a silicon alloy and a binder, characterized in that the binder has mechanical characteristics of a tensile strength of 50 N/mm2 or more, an elongation at break of 10% or more, a strain energy density of 2.5×10−3 J/mm3 or more and a coefficient of elasticity of 10000 N/mm2 or less, and preferably characterized in that the collector has mechanical characteristics of a tensile strength of 80 N/mm2 or more, a proportional limit 30 N/mm2 or more, an elongation at break of 1.0% or more and an elastic elongation limit of 0.03% or more.

Abstract translation: 一种锂二次电池用负极，其具有由导电性金属箔构成的集电体，在其表面上设有包含含有硅和/或硅合金的活性物质粒子和粘合剂的活性物质层，其特征在于，所述粘合剂 拉伸强度为50N / mm 2以上，断裂伸长率为10％以上，应变能​​密度为2.5×10 -3 J / mm 3以上，弹性系数为10000N / mm 2的机械特性 其特征在于，集电体的拉伸强度为80N / mm 2以上，比例范围为30N / mm 2以上，断裂伸长率为1.0％以上，弹性伸长极限为 0.03％以上。

公开(公告)号：US08195985B2

公开(公告)日：2012-06-05

申请号：US12718074

申请日：2010-03-05

Applicant: Hiroshi Nakamura ,  Hideki Matsuda ,  Fumiaki Akazawa ,  Makoto Shiraga

Inventor： Hiroshi Nakamura ,  Hideki Matsuda ,  Fumiaki Akazawa ,  Makoto Shiraga

IPC: G06F11/00

CPC classification number: G06F11/0748 ,  G06F11/0709 ,  G06F11/0772 ,  G06F11/0775 ,  H04L41/0213 ,  H04L43/06 ,  H04L43/0823

Abstract: A network monitor and control apparatus for controlling the monitoring of a network are provided. The network monitor includes an error monitor including an error information gatherer for gathering error information of a monitor target apparatus; and a monitor result notifier for notifying of monitor results, wherein if there are N types of monitor target functions, the error monitor includes N error information gatherers for the respective N types of monitor target functions (N=1, 2, 3, . . . ) and wherein each of the N error information gatherers gathers the error information from one of an existing monitor target apparatus and a newly added monitor target apparatus on a per monitor target function basis.

Abstract translation: 提供一种用于控制网络监控的网络监视和控制装置。 网络监视器包括错误监视器，其包括用于收集监视目标设备的错误信息的错误信息采集器; 以及用于通知监视器结果的监视器结果通知器，其中如果存在N种类型的监视目标功能，则所述错误监视器包括用于各N种类型的监视目标功能（N = 1,2,3，...，N）的N个错误信息采集器。 ），并且其中N个错误信息采集器中的每一个在每个监视目标功能的基础上从现有的监视目标设备和新添加的监视目标设备之一收集错误信息。

公开(公告)号：US20120091610A1

公开(公告)日：2012-04-19

申请号：US13334289

申请日：2011-12-22

Applicant: Hiroshi NAKAMURA ,  Junji Tsuboi ,  Shinji Souma

Inventor： Hiroshi NAKAMURA ,  Junji Tsuboi ,  Shinji Souma

IPC: B29C33/72 ,  B29C39/10 ,  B29C39/22

CPC classification number: G03G15/0812 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/31

Abstract: A method for manufacturing a developing blade including a blade member located along one side edge of a support member, comprising providing a top mold with a cavity, sandblasting the cavity with an abrasive in a range of #150 to #1000, clamping together the top mold and a bottom mold while the top mold is in alignment with the bottom mold while at least a part of the support member is positioned in the cavity, and pouring a molding material from a gate to fill the cavity.

Abstract translation: 一种用于制造包括沿着支撑构件的一个侧边缘设置的刀片构件的显影刀片的方法，包括提供具有空腔的上模具，用＃150至＃1000范围内的研磨剂对所述腔进行喷砂，将所述顶部 模具和底模，同时顶模与底模对准，而支撑构件的至少一部分位于空腔中，并且从浇口浇注模制材料以填充空腔。

公开(公告)号：US08154922B2

公开(公告)日：2012-04-10

申请号：US13100020

申请日：2011-05-03

Applicant: Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

Inventor： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract translation: 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

公开(公告)号：US20120075903A1

公开(公告)日：2012-03-29

申请号：US13310148

申请日：2011-12-02

Applicant: Hiroshi Watanabe ,  Hiroshi Nakamura ,  Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshitake Yaegashi ,  Yuji Takeuchi ,  Kenichi Imamiya ,  Ken Takeuchi ,  Hideko Oodaira

Inventor： Hiroshi Watanabe ,  Hiroshi Nakamura ,  Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshitake Yaegashi ,  Yuji Takeuchi ,  Kenichi Imamiya ,  Ken Takeuchi ,  Hideko Oodaira

IPC: G11C5/06

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract translation: 选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。 第一级导电层具有接触区域。 第二级导电层的部分被去除，位于接触区域上方。 在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。 一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

公开(公告)号：US08144513B2

公开(公告)日：2012-03-27

申请号：US12960882

申请日：2010-12-06

Applicant: Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

Inventor： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

公开(公告)号：US08129014B2

公开(公告)日：2012-03-06

申请号：US11952604

申请日：2007-12-07

Applicant: Hiroshi Nakamura ,  Junji Tsuboi ,  Shinji Souma

Inventor： Hiroshi Nakamura ,  Junji Tsuboi ,  Shinji Souma

IPC: B32B7/02

CPC classification number: G03G15/0812 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/31

Abstract: A developing blade (11) comprises a blade member (14) located along one side edge of a support member (12) and having a surface shape defined by a maximum height roughness Ry of 0.35 to 4.5 μm and a length ratio under load tp (at a 30% cut level) of 15% or less. Such a developing blade is manufactured by bringing a top mold (2) having a mold surface (2A) with a cavity (4) formed for the formation of a blade member and a gate (6) in communication with the cavity (4) in alignment with a bottom mold (3) having a flat mold surface (3A) such that at least a part of the support member (12) is positioned in the cavity (4), clamping together both the top and bottom molds, and pouring a molding material from the gate (6) to fill in the cavity (4).

Abstract translation: 显影刀片（11）包括沿着支撑构件（12）的一个侧边缘定位并且具有由0.35至4.5μm的最大高度粗糙度Ry和负载下的长度比tp（ 以30％的削减水平）为15％以下。 通过使具有模具表面（2A）的顶模（2）具有形成用于形成叶片构件的空腔（4）和与空腔（4）连通的浇口（6），从而制造这种显影刮板 与具有平坦模具表面（3A）的底部模​​具（3）对准，使得支撑构件（12）的至少一部分定位在空腔（4）中，将顶部和底部模具夹紧在一起并且倾倒 模制材料从浇口（6）填充到空腔（4）中。