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44 条记录 (耗时 0.021 秒)

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    21.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100081265A1

    公开(公告)日：2010-04-01

    申请号：US12557111

    申请日：2009-09-10

    申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Hidefumi Mukai ,  Fumiharu Nakajima ,  Chikaaki Kodama

    发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Hidefumi Mukai ,  Fumiharu Nakajima ,  Chikaaki Kodama

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11524 ,  H01L21/0337 ,  H01L21/32139

    摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.

    摘要翻译： 根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

    Wiring graphic verification method, program and apparatus
    22.
    发明申请
    Wiring graphic verification method, program and apparatus 失效
    接线图形验证方法，程序和设备

    公开(公告)号：US20050005252A1

    公开(公告)日：2005-01-06

    申请号：US10805478

    申请日：2004-03-22

    申请人： Chikaaki Kodama ,  Akiihiro Yoshitake

    发明人： Chikaaki Kodama ,  Akiihiro Yoshitake

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5081

    摘要： An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range. A slanted wiring edge extraction unit extracts slanted wiring edges which are in contact with graphics classified into the wiring width ranges, and a slanted wiring interval verification unit verifies intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

    摘要翻译： 边缘提取单元从整体布线图形中提取垂直和水平布线边缘和倾斜的布线边缘，并且布线宽度分类单元执行整个布线图形的缩放处理以将布线图形分类为由预定义的参考划分的布线宽度范围 接线宽度。 垂直和水平布线边缘提取单元提取与分类为布线宽度范围的图形接触的垂直和水平布线边缘，并且垂直和水平布线间隔验证单元验证垂直和水平布线边缘和相对边缘之间的间隔，以 基于每个布线宽度范围的垂直和水平参考间隔的验证对象。 倾斜的布线边缘提取单元提取与分类为布线宽度范围的图形相接触的倾斜布线边缘，并且倾斜布线间隔验证单元基于倾斜的参考间隔来验证倾斜的布线边缘和相对的边缘之间的间隔作为验证对象 对于每个接线宽度范围。

    Mask pattern generating method and computer program product
    23.
    发明授权
    Mask pattern generating method and computer program product 有权
    掩模图案生成方法和计算机程序产品

    公开(公告)号：US08609303B2

    公开(公告)日：2013-12-17

    申请号：US13237651

    申请日：2011-09-20

    申请人： Chikaaki Kodama ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

    发明人： Chikaaki Kodama ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

    IPC分类号： G03F1/38 ,  G03F1/68

    CPC分类号： G03F1/36 ,  G03F1/38

    摘要： According to a mask pattern generating method of the embodiments, an undesired pattern, which is transferred onto a substrate due to an auxiliary pattern when an on-substrate pattern is formed on the substrate by using a mask pattern in which the auxiliary pattern is placed, is extracted as an undesired transfer pattern. Then, the mask pattern is corrected by changing a size of the auxiliary pattern according to a size and a position of the undesired transfer pattern.

    摘要翻译： 根据实施例的掩模图案生成方法，当通过使用其中放置辅助图案的掩模图案在衬底上形成衬底上图案时，由于辅助图案而转移到衬底上的不需要的图案， 被提取为不期望的转移模式。 然后，通过根据不希望的转印图案的尺寸和位置改变辅助图案的尺寸来校正掩模图案。

    Original plate evaluation method, computer readable storage medium, and original plate manufacturing method
    24.
    发明授权
    Original plate evaluation method, computer readable storage medium, and original plate manufacturing method 有权
    原版评估方法，计算机可读存储介质和原版制版方法

    公开(公告)号：US08438527B2

    公开(公告)日：2013-05-07

    申请号：US13426965

    申请日：2012-03-22

    申请人： Satomi Nakamura ,  Toshiya Kotani ,  Kazuhito Kobayashi ,  Akiko Mimotogi ,  Chikaaki Kodama

    发明人： Satomi Nakamura ,  Toshiya Kotani ,  Kazuhito Kobayashi ,  Akiko Mimotogi ,  Chikaaki Kodama

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70 ,  G03F1/84 ,  G03F7/70625

    摘要： According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.

    摘要翻译： 根据一个实施例，公开了原版评估方法。 原版包括基板和N形图案，其形状彼此不同。 该方法包括基于第一准则从N个图案中选择N1个图案，获得N1个图案的测量值，执行所获得的测量值是否满足第一指定值，根据第二准则从N个图案中选择N2个图案，预测形状 对应于N2图案的传送图案，执行预测形状是否满足第二规格值的判定，以及基于该判定来评估印版。

    MASK-LAYOUT CREATING METHOD, APPARATUS THEREFOR, AND COMPUTER PROGRAM PRODUCT
    27.
    发明申请
    MASK-LAYOUT CREATING METHOD, APPARATUS THEREFOR, AND COMPUTER PROGRAM PRODUCT 有权
    掩模制作方法，其设备和计算机程序产品

    公开(公告)号：US20110209107A1

    公开(公告)日：2011-08-25

    申请号：US13028525

    申请日：2011-02-16

    申请人： Katsuyoshi KODERA ,  Chikaaki Kodama

    发明人： Katsuyoshi KODERA ,  Chikaaki Kodama

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.

    摘要翻译： 根据一个实施例，设置在光刻过程中很可能是危险点的设计布局，相对于集合设计布局设置用于生成掩模布局的相干映射内核，基于该集合创建相干映射 相干映射内核和集合设计布局，从创建的相干图中提取辅助模式并对其进行整形以生成掩模布局，定义用于评估掩模布局优化度的成本函数COST，使用 成本函数以及从相干图提取和整形辅助图案中的相干图核心和参数中的至少一个被改变，直到使用成本函数评估的掩模布局被优化为止。