公开(公告)号：US20130164934A1

公开(公告)日：2013-06-27

申请号：US13665803

申请日：2012-10-31

申请人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

发明人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US08347241B2

公开(公告)日：2013-01-01

申请号：US12354119

申请日：2009-01-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Chikaaki Kodama

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.

摘要翻译： 图案生成方法包括：通过第一处理获取要在过程目标胶片上形成的第一图案的第一设计约束，所述第一设计约束使用作为所述第一图案中的任意一个的图案宽度的索引，以及 任意图案之间的空间和与任意图案相邻的图案; 根据第二处理的图案转换来校正第一设计约束，从而获得第二图案的第二设计约束，该第二图案使用在第二图案的预定图案空间的两侧上的两个图案作为索引; 判断设计模式是否符合第二设计约束; 并且当不满足设计约束时，改变设计模式以对应于由第二设计约束允许的值。

公开(公告)号：US20120184109A1

公开(公告)日：2012-07-19

申请号：US13397750

申请日：2012-02-16

申请人： Hiromitsu MASHITA ,  Toshiya KOTANI ,  Fumiharu NAKAJIMA ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

发明人： Hiromitsu MASHITA ,  Toshiya KOTANI ,  Fumiharu NAKAJIMA ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

IPC分类号： H01L21/302

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

公开(公告)号：US08110413B2

公开(公告)日：2012-02-07

申请号：US12880487

申请日：2010-09-13

申请人： Chikaaki Kodama ,  Takanori Urakami ,  Nozomu Furuta ,  Shunsuke Kagaya

发明人： Chikaaki Kodama ,  Takanori Urakami ,  Nozomu Furuta ,  Shunsuke Kagaya

IPC分类号： H01L21/00 ,  G06F19/00 ,  H01R43/00

CPC分类号： G03F1/36 ,  Y10T29/49117

摘要： In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion.

摘要翻译： 在一个实施例中，公开了一种掩模图案验证装置。 掩模图案验证装置可以包括登记清洁电路图案的库登记部分，保存设计电路图案的存储部分，验证电路图案，验证掩模图案和验证晶片图案，进行掩模验证的掩模验证部分 验证掩模图案，对验证晶片图案执行光刻验证的光刻验证部分和包括将清洁电路图案注册到库登记部分的库登记电路的CPU，验证清除电路图案被设置的模式匹配电路 在设计电路图案中，从设计电路图案提取验证电路图案的验证图案提取电路，对验证电路图案执行OPC的OPC电路，控制掩模验证部分的掩模验证电路以及光刻验证电路控制 光刻验证部分。

公开(公告)号：US20110086515A1

公开(公告)日：2011-04-14

申请号：US12880487

申请日：2010-09-13

申请人： Chikaaki KODAMA ,  Takanori Urakami ,  Nozomu Furuta ,  Shunsuke Kagaya

发明人： Chikaaki KODAMA ,  Takanori Urakami ,  Nozomu Furuta ,  Shunsuke Kagaya

IPC分类号： H01L21/31 ,  G06F17/50

CPC分类号： G03F1/36 ,  Y10T29/49117

摘要： In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion.

摘要翻译： 在一个实施例中，公开了一种掩模图案验证装置。 掩模图案验证装置可以包括登记清洁电路图案的库登记部分，保存设计电路图案的存储部分，验证电路图案，验证掩模图案和验证晶片图案，进行掩模验证的掩模验证部分 验证掩模图案，对验证晶片图案执行光刻验证的光刻验证部分和包括将清洁电路图案注册到库登记部分的库登记电路的CPU，验证清除电路图案被设置的模式匹配电路 在设计电路图案中，从设计电路图案提取验证电路图案的验证图案提取电路，对验证电路图案执行OPC的OPC电路，控制掩模验证部分的掩模验证电路以及光刻验证电路控制 光刻验证部分。

公开(公告)号：US20100038795A1

公开(公告)日：2010-02-18

申请号：US12542540

申请日：2009-08-17

申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

公开(公告)号：US20090258503A1

公开(公告)日：2009-10-15

申请号：US12403740

申请日：2009-03-13

申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Fumiharu Nakajima ,  Takafumi Taguchi ,  Chikaaki Kodama

IPC分类号： H01L21/306

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

公开(公告)号：US07120881B2

公开(公告)日：2006-10-10

申请号：US10805478

申请日：2004-03-22

申请人： Chikaaki Kodama ,  Akiihiro Yoshitake

发明人： Chikaaki Kodama ,  Akiihiro Yoshitake

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range. A slanted wiring edge extraction unit extracts slanted wiring edges which are in contact with graphics classified into the wiring width ranges, and a slanted wiring interval verification unit verifies intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

摘要翻译： 边缘提取单元从整体布线图形中提取垂直和水平布线边缘和倾斜的布线边缘，并且布线宽度分类单元执行整个布线图形的缩放处理以将布线图形分类为由预定义的参考划分的布线宽度范围 接线宽度。 垂直和水平布线边缘提取单元提取与分类为布线宽度范围的图形接触的垂直和水平布线边缘，并且垂直和水平布线间隔验证单元验证垂直和水平布线边缘和相对边缘之间的间隔，以 基于每个布线宽度范围的垂直和水平参考间隔的验证对象。 倾斜的布线边缘提取单元提取与分类为布线宽度范围的图形相接触的倾斜布线边缘，并且倾斜布线间隔验证单元基于倾斜的参考间隔来验证倾斜的布线边缘和相对的边缘之间的间隔作为验证对象 对于每个接线宽度范围。

公开(公告)号：US08809072B2

公开(公告)日：2014-08-19

申请号：US13051961

申请日：2011-03-18

申请人： Chikaaki Kodama ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

发明人： Chikaaki Kodama ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G03F1/36

摘要： According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

摘要翻译： 根据实施例中的子分辨率辅助特征排列方法，选择规则库和模型库中的哪一个被设置为对应于主图案的图案数据上的哪个图案区域作为安排子图形的方法的类型， 分辨率辅助功能，用于提高在基板上形成的主图案的分辨率。 然后，将规则库的子分辨率辅助特征设置在设置为规则库的图案区域中，并且由模型库将子分辨率辅助特征排列在设置为模型库的图案区域中。

公开(公告)号：US20120241834A1

公开(公告)日：2012-09-27

申请号：US13234052

申请日：2011-09-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

摘要翻译： 根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。 基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。 当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径 的曝光装置为NA，处理参数为k1。 在绘图区域中匹配互连间隔的第二维大于第一维度。