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21.发明申请公开(公告)号：US20200295255A1
公开(公告)日：2020-09-17
申请号：US16890215
申请日：2020-06-02
发明人： Srinivas V. PIETAMBARAM , Bengt J. AKERMAN , Renu WHIG , Jason A. JANESKY , Nicholas D. RIZZO , Jon M. SLAUGHTER
摘要： A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (1) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may he disposed on the first layer.
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公开(公告)号：US20200286950A1
公开(公告)日：2020-09-10
申请号：US16881958
申请日：2020-05-22
摘要： Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号：US20200235288A1
公开(公告)日：2020-07-23
申请号：US16744963
申请日：2020-01-16
发明人： Sumio IKEGAWA , Han Kyu LEE , Sanjeev AGGARWAL , Jijun SUN , Syed M. ALAM , Thomas ANDRE
摘要： The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
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公开(公告)号：US10707410B2
公开(公告)日：2020-07-07
申请号：US16225670
申请日：2018-12-19
发明人： Srinivas V. Pietambaram , Bengt J. Akerman , Renu Whig , Jason A. Janesky , Nicholas D. Rizzo , Jon M. Slaughter
摘要： A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
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公开(公告)号：US10700123B2
公开(公告)日：2020-06-30
申请号：US16143088
申请日：2018-09-26
摘要： Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号：US20200176672A1
公开(公告)日：2020-06-04
申请号：US16695396
申请日：2019-11-26
IPC分类号： H01L43/04 , H01L43/14 , H01L21/3065
摘要： A magnetoresistive device may include an intermediate region positioned between a magnetically fixed region and a magnetically free region, and spin Hall channel region extending around a sidewall of at least the magnetically free region. An insulator region may extend around a portion of the sidewall such that the insulator region contacts a first portion of the sidewall and the spin Hall channel region contacts a second portion of the sidewall.
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公开(公告)号：US10658576B2
公开(公告)日：2020-05-19
申请号：US16580025
申请日：2019-09-24
摘要： A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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公开(公告)号：US10658013B2
公开(公告)日：2020-05-19
申请号：US16252067
申请日：2019-01-18
发明人： Thomas Andre , Syed M. Alam , Frederick Neumeyer
摘要： The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
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公开(公告)号：US10657065B2
公开(公告)日：2020-05-19
申请号：US16359514
申请日：2019-03-20
IPC分类号： G06F12/00 , G06F12/0893 , G06F3/06 , G06F12/0802 , G06F12/0862 , G11C7/10 , G11C7/22 , G11C16/32 , G11C11/16 , G06F12/02 , G06F12/0804 , G06F12/0846 , G06F12/0855
摘要： A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
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公开(公告)号：US10608648B2
公开(公告)日：2020-03-31
申请号：US16277557
申请日：2019-02-15
发明人： Jieming Qi , Aaron D. Willey
摘要： Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.
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