公开(公告)号：US09779815B2

公开(公告)日：2017-10-03

申请号：US15221318

申请日：2016-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/788 ,  H01L27/11526

CPC classification number: G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/7883

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

公开(公告)号：US09753665B2

公开(公告)日：2017-09-05

申请号：US15053950

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G11C5/066 ,  G11C7/10 ,  G11C8/12

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

公开(公告)号：US09747053B1

公开(公告)日：2017-08-29

申请号：US15221343

申请日：2016-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/12

Abstract: A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.

公开(公告)号：US09729202B2

公开(公告)日：2017-08-08

申请号：US15198758

申请日：2016-06-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Alexandre Tramoni ,  Pierre Rizzo

IPC: H04B5/00 ,  H03H7/40 ,  H04W76/02

CPC classification number: H04B5/0031 ,  H03H7/40 ,  H04W76/14

Abstract: A first component (CMP1) is connected to the antenna (ANT) and to an impedance matching circuit (CAI) configurable on command and connected to the antenna, and in the absence of another component (CMP2) connected to the antenna, the impedance matching circuit is placed in a first configuration in which it forms with the first component and the antenna a resonant circuit having a first resonant frequency compatible with a carrier frequency. In the presence of a second component (CMP2) connected to the antenna, the impedance matching circuit is placed in a second configuration in which it forms with the first component, the second component and the antenna a resonant circuit having a second resonant frequency compatible with the carrier frequency.

公开(公告)号：US09729199B2

公开(公告)日：2017-08-08

申请号：US14984966

申请日：2015-12-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark Wallis ,  Yoann Bouvet ,  Pierre Demaj

IPC: H04B3/54 ,  H04L27/26 ,  H04L5/00 ,  H04L25/03 ,  H04L25/06

CPC classification number: H04B3/54 ,  H04L5/0007 ,  H04L25/03993 ,  H04L25/067 ,  H04L27/2607 ,  H04L27/2656 ,  H04L27/2675 ,  H04L27/2691

Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.

公开(公告)号：US09710650B2

公开(公告)日：2017-07-18

申请号：US14668692

申请日：2015-03-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: G06F21/57 ,  G06F12/14 ,  G06F21/55 ,  G01K13/00 ,  G06F21/71

CPC classification number: G06F21/575 ,  G01K13/00 ,  G06F12/1458 ,  G06F21/554 ,  G06F21/71 ,  G06F2212/1052 ,  G06F2221/034 ,  G06F2221/2137

Abstract: A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.

公开(公告)号：US09705533B2

公开(公告)日：2017-07-11

申请号：US14961985

申请日：2015-12-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark Wallis

IPC: H04B1/00 ,  H04L5/00 ,  H04B3/54

CPC classification number: H04B1/0007 ,  H04B3/54 ,  H04B2203/5425 ,  H04L5/001

Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.

公开(公告)号：US09689659B2

公开(公告)日：2017-06-27

申请号：US14509920

申请日：2014-10-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Maxime Teissier ,  Cyril Troise

IPC: G01B7/14 ,  G01V3/08 ,  H03K17/945 ,  H03K17/955 ,  G01B7/00

CPC classification number: G01B7/14 ,  G01B7/003 ,  G01V3/088 ,  H03K17/945 ,  H03K17/955 ,  H03K2217/960705

Abstract: The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold.

公开(公告)号：US20170179247A1

公开(公告)日：2017-06-22

申请号：US15454184

申请日：2017-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/423 ,  H01L21/311 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/28167 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

公开(公告)号：US09661448B2

公开(公告)日：2017-05-23

申请号：US14956501

申请日：2015-12-02

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Alexandre Charles

IPC: H04B5/00 ,  H04W4/00 ,  H04L9/08 ,  G06K7/10 ,  H04L12/933

CPC classification number: H04W4/008 ,  G06K7/10237 ,  H04B5/00 ,  H04B5/0031 ,  H04B5/0056 ,  H04L49/102 ,  H04W4/80

Abstract: A method is for managing information communication between an NFC controller coupled to an antenna for a contactless communication with an object, a device host, and a secure element. The method may include routing the information through the NFC controller, and communicating first information to be communicated between the secure element and the device host through a first communication link between the NFC controller and the device host, and through a second communication link between the NFC controller and the secure element. The method may include communicating second information with the antenna through a third communication link between the NFC controller and the secure element, the first and second communication links having bandwidths greater than a bandwidth of the third communication link.