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    Level shift circuit
    11.
    发明授权
    Level shift circuit 失效
    电平移位电路

    公开(公告)号：US06963238B2

    公开(公告)日：2005-11-08

    申请号：US10849200

    申请日：2004-05-20

    Applicant: Kouji Mochizuki

    Inventor： Kouji Mochizuki

    IPC: H03M1/74 ,  H03F3/45 ,  H03K5/08 ,  H03L5/00 ,  H03M1/10 ,  H03M1/66 ,  H03M1/70

    CPC classification number: H03F3/45475 ,  H03F3/45941 ,  H03F3/45959 ,  H03F2203/45212 ,  H03F2203/45588

    Abstract: A high-precision and high-performance level shift circuit, which is not adversely influenced by an offset error owned by an operational amplifier. Two sets of resistors (4o) and (4p) having the same resistance values, which are connected between differential output terminals and an operational amplifier (4r) for performing a level shift control are provided. A feedback operation is carried out in such a manner that an average voltage of each of differential outputs (4i) and (4m) is continuously made coincident with a DC reference potential (4q) irrespective of an offset error of an output-purpose operational amplifier, and a level shift function having a small error is realized. Two resistors (4h and 4l) are series-connected between a differential output of a digital/analog converter (4a) and a level shift circuit to output a voltage outside an output dynamic range of the digital/analog converter (4a).

    Abstract translation: 高精度，高性能的电平移位电路，不受运算放大器拥有偏移误差的不利影响。 提供两组具有相同电阻值的电阻器（4o）和（4p），其连接在差分输出端子和用于执行电平转换控制的运算放大器（4r）之间。 执行反馈操作，使得差分输出（4i）和（4m）中的每一个的平均电压连续地与DC参考电位（4q）一致，而不管输出 - 输出的偏移误差如何， 实现了目的运算放大器和具有小误差的电平移位功能。 两个电阻器（4h和4l）串联连接在数/模转换器（4a）的差分输出端和电平移位电路之间，以输出数/模转换器（4a）的输出动态范围之外的电压 ）。

    Amplifier apparatus and magnetic recording and reproducing apparatus having the same
    12.
    发明申请
    Amplifier apparatus and magnetic recording and reproducing apparatus having the same 失效
    具有该放大器装置和磁记录和再现装置

    公开(公告)号：US20040125480A1

    公开(公告)日：2004-07-01

    申请号：US10717544

    申请日：2003-11-21

    Inventor： Kazue Takayoshi ,  Michiya Sako

    IPC: G11B005/09 ,  G11B005/02

    CPC classification number: H03F3/45959 ,  G11B5/012 ,  G11B5/59605 ,  G11B5/59622 ,  G11B2005/001 ,  G11B2005/0016 ,  G11B2005/0018

    Abstract: Provides a magnetic recording and reproducing apparatus having an amplified apparatus, which is switched from a recording state to a readout state based on a control signal; reads out a signal containing a servo signal by the signal readout means; and includes the amplifier apparatus for amplifying the signal with an amplifier and outputting the amplified signal; and filters the signals by the filtering means that allows high frequency part of signals to pass through with the first cutoff frequency during the first prescribed time period after the readout state has been initiated; the second cutoff frequency that is lower than the first cutoff frequency during the second prescribed time period after the first prescribed time period has passed; and the third cutoff frequency that is lower than the second cutoff frequency after the second prescribed time period has passed.

    Abstract translation: 提供具有放大装置的磁记录和再现装置，其根据控制信号从记录状态切换到读出状态; 通过信号读出装置读出含有伺服信号的信号; 并且包括用放大器放大信号并输出​​放大信号的放大器装置; 并且通过滤波装置对信号进行滤波，该滤波装置允许高频部分的信号在读出状态已经开始之后的第一规定时间段期间通过第一截止频率; 在经过第一规定时间之后的第二规定时间段内低于第一截止频率的第二截止频率; 并且在经过第二规定时间段之后低于第二截止频率的第三截止频率。

    Base band filter including a semiconductor integrated circuit
    13.
    发明授权
    Base band filter including a semiconductor integrated circuit 有权
    基带滤波器包括半导体集成电路

    公开(公告)号：US06664854B2

    公开(公告)日：2003-12-16

    申请号：US10232722

    申请日：2002-09-03

    Applicant: Satoshi Tanaka ,  Shigetaka Takagi ,  Nobuo Fujii

    Inventor： Satoshi Tanaka ,  Shigetaka Takagi ,  Nobuo Fujii

    IPC: H03F345

    CPC classification number: H03F3/45959 ,  H03F3/45291 ,  H03F3/45946 ,  H03F2200/372 ,  H03H11/0422 ,  H03H2011/0494

    Abstract: When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circuits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.

    Abstract translation: 当要被放大的输入信号非常小并且具有高频率的大阻塞信号被包括在输入中时，移动通信用滤波器需要去除共模信号抑制比大。 此外，即使在具有高增益的放大器的情况下，为了避免放大器的噪声饱和，优选地，共模抑制比较大。 通过由Nauta差分电路提出的积分电路的输入的跨导电路和其交叉连接来将共模抑制特性添加到输入级。 因此，通过应用于CMOS工艺或BiCMOS工艺来实现滤波器以及提高总共模抑制比的放大器。

    Line terminal circuit for controlling the common mode voltage level on a transmission line
    14.
    发明授权
    Line terminal circuit for controlling the common mode voltage level on a transmission line 有权
    线路终端电路，用于控制传输线上的共模电压电平

    公开(公告)号：US06654462B1

    公开(公告)日：2003-11-25

    申请号：US09331634

    申请日：1999-10-04

    Applicant: Mats Hedberg

    Inventor： Mats Hedberg

    IPC: H04M100

    CPC classification number: H04L25/0276 ,  H03F3/45959 ,  H04B3/30 ,  H04L25/028 ,  H04L25/0292

    Abstract: A line terminal circuit comprises a buffer section (A, D) for connection to a transmission line (TL) and for performing at least one of the functions receiving signals from said transmission line and transmitting signals via said transmission line; a controllable current source section (S1, S2) connected to inject or withdraw a current (Iu, Id) into or from a node (ND1, ND2) between said buffer section and said transmission line in accordance with a current control signal (CS); and a common mode voltage control section (CT) for detecting a common mode voltage component on the transmission line (TL) connected to the buffer section (A, D) and for generating said current control signal (CS) in response to said detected common mode voltage component and outputting said current control signal to said current source section (S1, S2); said common mode voltage control section (CT) being adapted to output said current control signal (CS) such that said common mode voltage component is within the limits of a predetermined voltage interval (Vrefh, Vrefl).

    Abstract translation: 线路终端电路包括用于连接到传输线（TL）的缓冲器部分（A，D），并且用于执行从所述传输线接收信号的功能中的至少一个，并且经由所述传输线路传输信号; 连接用于根据电流控制信号（CS）将所述缓冲器部分和所述传输线路之间的节点（ND1，ND2）注入或退出电流（Iu，Id）的可控电流源部分（S1，S2） ; 以及共模电压控制部分（CT），用于检测连接到缓冲器部分（A，D）的传输线（TL）上的共模电压分量，并响应于所检测到的公共端产生所述电流控制信号（CS） 模式电压分量，并将所述电流控制信号输出到所述电流源部分（S1，S2）; 所述共模电压控制部分（CT）适于输出所述电流控制信号（CS），使得所述共模电压分量在预定电压间隔（Vrefh，Vrefl）的限度内。

    Semiconductor integrated circuit
    15.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20030052738A1

    公开(公告)日：2003-03-20

    申请号：US10232722

    申请日：2002-09-03

    Applicant: Hitachi, Ltd.

    Inventor： Satoshi Tanaka ,  Shigetaka Takagi ,  Nobuo Fujii

    IPC: H03F003/45

    CPC classification number: H03F3/45959 ,  H03F3/45291 ,  H03F3/45946 ,  H03F2200/372 ,  H03H11/0422 ,  H03H2011/0494

    Abstract: When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circuits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.

    Abstract translation: 当要被放大的输入信号非常小并且具有高频率的大阻塞信号被包括在输入中时，移动通信用滤波器需要去除共模信号抑制比大。 此外，即使在具有高增益的放大器的情况下，为了避免放大器的噪声饱和，优选地，共模抑制比较大。 通过由Nauta差分电路提出的积分电路的输入的跨导电路和其交叉连接来将共模抑制特性添加到输入级。 因此，通过应用于CMOS工艺或BiCMOS工艺来实现滤波器以及提高总共模抑制比的放大器。

    Differential amplifier apparatus
    16.
    发明授权
    Differential amplifier apparatus 失效
    差分放大器装置

    公开(公告)号：US5095282A

    公开(公告)日：1992-03-10

    申请号：US572478

    申请日：1990-08-23

    Applicant: Birney D. Dayton

    Inventor： Birney D. Dayton

    IPC: H03F3/347 ,  H03F3/45

    CPC classification number: H03F3/45973 ,  H03F3/347 ,  H03F3/45475 ,  H03F3/45959

    Abstract: Differential amplifier apparatus comprises a summing and inverting network for developing an output signal of which the magnitude is proportional to the common mode component of an input signal received at first and second input terminals of the apparatus and of which the polarity is opposite the polarity of the common mode component. A summing network is connected to the first and second input terminals and to the output of the summing and inverting network and has first and second intermediate nodes. A first differential amplifier has a non-inverting input connected to a first intermediate node of the summing network, and a second differential amplifier has a non-inverting input connected to the second intermediate node of the summing network. A bridging resistor is connected between the inverting inputs of the first and second differential amplifiers.

    Abstract translation: 差分放大器装置包括一个求和和反相网络，用于产生一个输出信号，该输出信号的幅度与在装置的第一和第二输入端接收的输入信号的共模分量成比例，并且其极性与 共模组件。 求和网络连接到第一和第二输入端和相加和反相网络的输出，并具有第一和第二中间节点。 第一差分放大器具有连接到求和网络的第一中间节点的非反相输入，并且第二差分放大器具有连接到求和网络的第二中间节点的非反相输入。 桥接电阻连接在第一和第二差分放大器的反相输入端之间。

    Level shift circuit
    19.
    发明申请
    Level shift circuit 失效
    电平移位电路

    公开(公告)号：US20040232970A1

    公开(公告)日：2004-11-25

    申请号：US10849200

    申请日：2004-05-20

    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.

    Inventor： Kouji Mochizuki

    IPC: H03L005/00

    CPC classification number: H03F3/45475 ,  H03F3/45941 ,  H03F3/45959 ,  H03F2203/45212 ,  H03F2203/45588

    Abstract: A high-precision and high-performance level shift circuit is provided, which is not adversely influenced by an offset error owned by an operational amplifier, and an output dynamic range of a digital/analog converter of a signal source. Since two sets of resistors 4o and 4p having the same resistance values to each other, which are connected between differential output terminals, and also, an operational amplifier 4r for performing a level shift control are provided, a feedback operation is carried out in such a manner that an average voltage of each of differential outputs 4i and 4m is continuously made coincident with a DC reference potential 4q irrespective of an offset error of an output-purpose operational amplifier, and a level shift function having a small error is realized. Also, since a resistor 4h and another resistor 4l are series-connected between a differential output of a digital/analog converter 4a and a level shift circuit, such a voltage can be outputted outside an output dynamic range of the digital/analog converter 4a.

    Abstract translation: 提供了高精度和高性能的电平移位电路，其不受运算放大器所拥有的偏移误差和信号源的数/模转换器的输出动态范围的不利影响。 由于提供两组电阻器4o和4p，它们彼此之间具有相同的电阻值，它们连接在差分输出端子之间，并且还提供了用于执行电平变换控制的运算放大器4r，这样的反馈操作 使得差分输出4i和4m中的每一个的平均电压连续地与DC参考电位4q一致，而与输出目的运算放大器的偏移误差无关，并且实现了具有小误差的电平偏移函数。 此外，由于电阻器4h和另一个电阻器41串联连接在数/模转换器4a的差分输出端与电平移位电路之间，所以这种电压可以被输出到数/模转换器4a的输出动态范围之外。

    Signal amplifier and optical signal receiver using the same
    20.
    发明授权
    Signal amplifier and optical signal receiver using the same 有权

    公开(公告)号：US06587004B2

    公开(公告)日：2003-07-01

    申请号：US10171559

    申请日：2002-06-12

    Applicant: Satoshi Ide

    Inventor： Satoshi Ide

    IPC: H03F308

    CPC classification number: H04B10/6933 ,  H03F3/087 ,  H03F3/45959 ,  H03F3/45982 ,  H03G3/3084 ,  H04B10/6931

    Abstract: To provide configuration of a signal amplifier and an optical signal receiver using the same, enabling to solve a problem of waveform deterioration being produced by external noise, etc. in the signal amplifier of the optical signal receiver. The optical signal receiver includes a first master-slave level detector for detecting a DC level of a normal phase signal, and a second master-slave level detector for detecting a DC level of an inverse phase signal. By adding alternated signal components respectively, a differential signal transmission is enabled. Accordingly, using two master-slave level detector having mutually symmetric configurations and thus enabling differential transmission, there can be obtained a signal amplifier which can cope with various transient responses produced at the top of a burst cell and is sufficiently protected against the disturbance produced by external noises.

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