Abstract:
A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
Abstract:
Provided is an optical receiver module which includes a conversion unit which converts an input optical signal to an electrical signal, an amplification unit which amplifies the electrical signal and outputs an amplified signal, a reception unit which directly or indirectly receives the amplified signal, and an offsetting unit which offsets the electrical signal such that a difference between a center of an intensity width of the electrical signal and a center of an intensity range of a signal capable of being received by the reception unit becomes small.
Abstract:
An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.
Abstract:
A TIA comprises a TIA core that converts a current signal to a voltage signal, a single-to-differential converter that generates a differential voltage signal from the voltage signal, a feedback circuit that generates a control signal from the differential voltage signal, a bypass circuit that generates the current signal by subtracting the bypass current from the input current so that an average value of the current signal is maintained at a predetermined value, and a monitor circuit that generates a monitor current proportional to the bypass current from the control signal
Abstract:
An amplifier for an optical receiver is disclosed. The amplifier includes a common base buffer, a differential amplifier, and some buffer amplifiers, where circuit block from the common base buffer to the buffer amplifiers have the differential arrangement and are connected in series in this order. The amplifier further includes an offset compensator that receives the outputs of the buffer amplifier put in the rear end of the amplifier and outputs control signals, which are complementary to each other and filtered by a low-pass-filter, to the base of the transistors in the common base buffer to compensate the offset appeared in the output of the buffer amplifier.
Abstract:
An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
Abstract:
Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.
Abstract:
The aim of the invention, which concerns a method and a system for converting an optical received pulse train into an electrical output pulse train, is to create a method and an associated circuit arrangement for converting an optical received pulse train into an electrical output pulse train whereby achieving an improvement in transmission quality and a reduction in latency time. According to the invention, the aim, with regard to the method, is achieved by virtue of the fact that: the current pulse train is converted in a controlled manner into a first voltage pulse train; the first voltage pulse train is converted into a second voltage pulse train by controllably limiting its amplitude; according to the amplitude of the second voltage pulse train, a third voltage pulse train, which is free from a static offset of the second voltage pulse train, is generated so that it is lower than a first amplitude quantity, and the third voltage pulse train, which is free from a dynamic offset, is generated so that it is greater than a second amplitude quantity that is greater than the first amplitude quantity; in the event of a packet pause, the amplitude of the third voltage pulse train is set to zero, and; the output pulse train is generated from the third voltage pulse train.
Abstract:
A control device with a switchable bandwidth including: an integrating element with a first capacitance, which is charged and discharged by at least one current; at least one second capacitance, which can be connected in parallel with the first capacitance via a first switch; and at least one voltage follower, via which the voltage present at the first capacitance can be fed to the second capacitance. In this case, the first switch is open if the voltage present at the first capacitance is fed to the second capacitance by means of the voltage follower. The first switch is closed if the second capacitance is connected in parallel with the first capacitance. The invention enables a further capacitance to be supplementarily connected without a disturbance signal arising.
Abstract:
An optical receiver circuit is constructed to be immune to interference from external interference signals. The optical receiver circuit includes a differential amplifier having an optical reception device connected to one input of the differential amplifier. The optical receiver circuit also includes an electrical element for simulating the electrical behavior of the reception device in the illumination-free state. The electrical element is connected to the other input of the differential amplifier.