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公开(公告)号:US20230397503A1
公开(公告)日:2023-12-07
申请号:US17874593
申请日:2022-07-27
发明人: CHIH-WEN TANG , Chih-Huang LAI , Wei-Chih HUANG , Chun-Liang YANG , Kuan-Ling OU
CPC分类号: H01L43/10 , H01L27/222 , H01L43/02 , H01F10/3268 , H01F10/3254 , H01F10/3286 , C22C38/10
摘要: Provided is a ferromagnetic free layer, comprising Fe, Co, B and an additive metal, and based on a total atomic number of the ferromagnetic free layer, a content of Co is more than 0 at % and less than 30 at %, a content of B is more than 10 at % and less than or equal to 35 at %, and a content of the additive metal is more than or equal to 2 at % and less than 10 at %; the additive metal comprises Mo, Re or a combination thereof, and a thickness of the ferromagnetic free layer is more than or equal to 1.5 nm and less than 2.5 nm. The ferromagnetic free layer can be applied to a MTJ structure as a single layer, and has sufficient thermal stability for maintaining good magnetic properties after thermal treatment, which makes sure that the MTJ structure can exert normal recording function.
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12.
公开(公告)号:US20230307029A1
公开(公告)日:2023-09-28
申请号:US18048121
申请日:2022-10-20
发明人: Alan KALITSOV , Derek STEWART , Bhagwati PRASAD
CPC分类号: G11C11/161 , H01L27/222 , H01L43/02 , H01L43/10 , G11C11/1673 , G11C11/1675
摘要: A magnetoresistive memory cell includes a first terminal electrode, a second terminal electrode, and a magnetoresistive layer stack located between the first terminal electrode and the second terminal electrode and including, from one side to another, a reference layer, a dielectric tunnel barrier layer, a free layer, and a material layer having two different states of lattice deformation which have different average in-plane lattice constants and which are configured to apply different in-plane stress. The material layer may be a metal-insulator transition (MIT) material layer that exhibits a phase transition between an insulator state and a metal state.
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13.
公开(公告)号:US20230307028A1
公开(公告)日:2023-09-28
申请号:US17656310
申请日:2022-03-24
发明人: Alan KALITSOV , Derek STEWART , Ananth KAUSHIK , Gerardo BERTERO
CPC分类号: G11C11/161 , H01F10/3286 , G11C11/1675 , G11C11/1673 , H01L43/08 , H01L43/10 , H01L43/02 , H01L27/222 , G01R33/093
摘要: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.
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公开(公告)号:US20230301205A1
公开(公告)日:2023-09-21
申请号:US17943763
申请日:2022-09-13
申请人: Kioxia Corporation
发明人: Taichi IGARASHI , Yuichi ITO , Eiji KITAGAWA
CPC分类号: H01L45/165 , H01L45/1253 , H01L45/141 , H01L45/1233 , H01L43/08 , H01L43/02 , G11C11/161 , H01L27/222 , H01L27/2463
摘要: According to one embodiment, a switching element includes a first electrode, a second electrode, and a switching material layer provided between the first electrode and the second electrode. The switching material layer contains silicon (Si), oxygen (O), arsenic (As), and a predetermined element selected from lead (Pb), silver (Ag), indium (In), tin (Sn), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), selenium (Se), antimony (Sb), tellurium (Te), gold (Au) and bismuth (Bi).
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公开(公告)号:US20230298647A1
公开(公告)日:2023-09-21
申请号:US17843084
申请日:2022-06-17
申请人: Kioxia Corporation
发明人: Kuniaki SUGIURA , Taichi IGARASHI
CPC分类号: G11C11/161 , G11C11/1675 , H01L27/222 , H01L43/02 , H01L43/12
摘要: According to one embodiment, a memory device includes: a first memory cell; a second memory cell; a first circuit configured to supply a write current to the first memory cell and the second memory cell; a first wiring coupled to the first circuit; a first electrode configured to electrically couple the first memory cell to the first wiring; and a second electrode configured to electrically couple the second memory cell to the first wiring. A length of the first wiring from the first circuit to the first electrode is smaller than a length of the first wiring from the first circuit to the second electrode. A resistance value of the first electrode is higher than a second resistance value of the second electrode.
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公开(公告)号:US20230263074A1
公开(公告)日:2023-08-17
申请号:US17747757
申请日:2022-05-18
发明人: MingYuan Song , Chien-Min Lee , Xinyu Bao
CPC分类号: H01L43/04 , H01L27/222 , H01L43/06 , H01L43/10 , H01L43/14
摘要: A magnetic memory device including bottom electrode bridges and a spin-orbit torque structure overlapping and physically coupled to the bottom electrode bridges and a method of forming the same are disclosed. In an embodiment, a memory includes a first electrode on a first via; a second electrode on a second via; a spin-orbit torque (SOT) structure physically and electrically coupled to the first electrode and the second electrode, the SOT structure overlapping the first electrode and the second electrode; and a magnetic tunnel junction (MTJ) on the SOT structure.
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公开(公告)号:US20230262992A1
公开(公告)日:2023-08-17
申请号:US17651169
申请日:2022-02-15
发明人: Ruilong Xie , Kangguo Cheng , Julien Frougier
IPC分类号: H01L27/22 , H01L23/522 , H01L23/528 , H01L43/02 , H01L43/12
CPC分类号: H01L27/222 , H01L23/5226 , H01L23/5283 , H01L43/02 , H01L43/12
摘要: A semiconductor component includes a first metal layer, a second metal layer, and an MRAM cell. The MRAM cell has a height that is equal to a distance between the first metal layer and the second metal layer. The semiconductor component further includes a first via layer, a third metal layer, and a second via layer. The first via layer, the third metal layer, and the second via layer have a combined height that is equal to the MRAM cell height.
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公开(公告)号:US20230223063A1
公开(公告)日:2023-07-13
申请号:US17571945
申请日:2022-01-10
发明人: Chih-Chuan SU , Yu-Jen WANG , Liang-Wei WANG , Dian-Hau CHEN
CPC分类号: G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
摘要: A semiconductor memory structure includes bottom electrodes formed over a substrate. The structure also includes first magnetic tunneling junction (MTJ) elements formed over the bottom electrodes in a first region and a second region of the substrate. The structure also includes second MTJ elements formed over the first MTJ elements in the first region and the second region. The structure also includes top electrodes formed over the second MTJ elements. The first MTJ elements in the first region are narrower than the second MTJ elements in the first region, and the second MTJ elements in the second region are narrower than the first MTJ elements in the second region.
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公开(公告)号:US20230217837A1
公开(公告)日:2023-07-06
申请号:US17593874
申请日:2021-03-09
发明人: YuLei WU , Baolei WU , Xiaoguang WANG , Er-Xuan PING
CPC分类号: H01L43/02 , H01L27/222 , H01L43/12
摘要: A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.
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公开(公告)号:US20230200258A1
公开(公告)日:2023-06-22
申请号:US17574569
申请日:2022-01-13
发明人: Hung-Chan Lin
CPC分类号: H01L43/14 , H01L27/222 , H01L43/04 , H01L43/06
摘要: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic random access memory (MRAM) region and a logic region, forming a first inter-metal dielectric (1MB) layer on the substrate, forming a first metal interconnection and a second metal interconnection in the first IMD layer on the MRAM region, forming a spin orbit torque (SOT) layer on the first metal interconnection and the second metal interconnection, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, forming a hard mask on the MTJ stack, using the hard mask to pattern the MTJ stack for forming the MTJ, forming the cap layer on the SOT layer and the hard mask, and patterning the cap layer and the SOT layer.
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