-
公开(公告)号：US20210118484A1
公开(公告)日：2021-04-22
申请号：US16709944
申请日：2019-12-11
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4074 , G11C11/4099 , G11C11/419
摘要： A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.
-
公开(公告)号：US10957409B1
公开(公告)日：2021-03-23
申请号：US16792304
申请日：2020-02-17
发明人： Xinlei Jia , Shan Li , Yali Song , Lei Jin , Hongtao Liu , Jianquan Jia , XiangNan Zhao , Yuan-Yuan Min
摘要： A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.
-
13.发明授权公开(公告)号：US11848058B2
公开(公告)日：2023-12-19
申请号：US18118565
申请日：2023-03-07
发明人： Yali Song , Jianquan Jia , Kaikai You , An Zhang , Xiangnan Zhao , Ying Cui , Shan Li , Kaiwei Li , Lei Jin , Xueqing Huang , Meng Lou , Jinlong Zhang
CPC分类号： G11C16/3427 , G11C16/0483 , H10B41/27 , H10B43/27
摘要： A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.
-
公开(公告)号：US11710529B2
公开(公告)日：2023-07-25
申请号：US17871472
申请日：2022-07-22
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
-
公开(公告)号：US11676665B2
公开(公告)日：2023-06-13
申请号：US17485241
申请日：2021-09-24
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
CPC分类号： G11C16/14 , G11C16/3445 , G11C16/0483
摘要： A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.
-
公开(公告)号：US20220215888A1
公开(公告)日：2022-07-07
申请号：US17186456
申请日：2021-02-26
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
-
公开(公告)号：US20220013177A1
公开(公告)日：2022-01-13
申请号：US17485241
申请日：2021-09-24
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
摘要： A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.
-
公开(公告)号：US11222674B2
公开(公告)日：2022-01-11
申请号：US16740491
申请日：2020-01-13
发明人： Shan Li , Kaikai You , Ying Cui , Jianquan Jia , Kaiwei Li , An Zhang
IPC分类号： G11C8/14 , G11C8/08 , G11C7/14 , G11C11/4074 , G11C11/4094 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/30
摘要： A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.
-
公开(公告)号：US20210174885A1
公开(公告)日：2021-06-10
申请号：US17180689
申请日：2021-02-19
发明人： Xinlei Jia , Shan Li , Yali Song , Lei Jin , Hongtao Liu , Jianquan Jia , XiangNan Zhao , Yuan-Yuan Min
摘要： A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines. The memory device further includes a word line driver coupled to the control circuit and the word lines and configured to, in response to the control signal, apply a positive first voltage signal to each of the word lines that are coupled to the gate terminals of the top memory cells during a first time period in a pre-charge phase prior to a programming phase.
-
20.发明申请公开(公告)号：US20210174852A1
公开(公告)日：2021-06-10
申请号：US16740491
申请日：2020-01-13
发明人： Shan Li , Kaikai You , Ying Cui , Jianquan Jia , Kaiwei Li , An Zhang
IPC分类号： G11C8/08 , G11C8/14 , G11C11/4074 , G11C11/4094 , G11C7/14
摘要： A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.
-
-
-
-
-
-
-
-
-
搜索结果
48 条记录 (耗时 0.028 秒)
