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公开(公告)号：US10038545B1
公开(公告)日：2018-07-31
申请号：US15660397
申请日：2017-07-26
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Winson Lin , Yu Xu , Geoffrey Zhang
CPC classification number: H04L7/0025 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0004 , H04L7/0012 , H04L7/033 , H04L7/0334 , H04L7/0337 , H04L7/0338 , H04L43/028 , H04L43/16
Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.
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12.发明授权Channel adaptive receiver switchable from a digital-based receiver mode to an analog-based receiver mode 有权信道自适应接收机可以从基于数字的接收机模式切换到基于模拟的接收机模式公开(公告)号：US09178552B1
公开(公告)日：2015-11-03
申请号：US14547394
申请日：2014-11-19
Applicant: Xilinx, Inc.
Inventor： Patrick Satarzadeh , Hongtao Zhang , Geoffrey Zhang , Zhaoyin D. Wu
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/03057 , H04L2025/03547
Abstract: In a method for channel adaptation, an analog input signal is received with a bimodal receiver via a communications channel. The analog input signal is converted to a digital input signal with an analog-to-digital converter of a digital receiver of the bimodal receiver. Channel coefficients are detected for the digital input signal associated with the communications channel. The channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized digital output signal from the digital input signal. It is determined whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number. A switch from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver is made to provide the equalized digital output signal for the analog input signal.
Abstract translation: 在一种用于信道适配的方法中，通过通信信道用双模接收机接收模拟输入信号。 模拟输入信号通过双模接收器的数字接收器的模数转换器转换为数字输入信号。 检测与通信信道相关联的数字输入信号的信道系数。 信道系数指示用于从数字输入信号提供均衡的数字输出信号的双模接收机的多个后置光标抽头。 确定后视标抽头的数量或与其相关联的值是否等于或小于阈值数。 使得从数字接收机将模拟输入信号接收到双模接收机的模拟接收机的切换是为模拟输入信号提供均衡的数字输出信号。
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公开(公告)号：US10348310B1
公开(公告)日：2019-07-09
申请号：US15992646
申请日：2018-05-30
Applicant: Xilinx, Inc.
Inventor： Karim M. Megawer , Parag Upadhyaya , Didem Z. Turker Melek , Zhaoyin D. Wu
Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.
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公开(公告)号：US09882795B1
公开(公告)日：2018-01-30
申请号：US14689327
申请日：2015-04-17
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Xu , Patrick Satarzadeh , Zhaoyin D. Wu
CPC classification number: H04L43/0811 , H04L7/0087 , H04L25/03057
Abstract: In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.
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Patent Agency Ranking
公开(公告)号：US09800438B1
公开(公告)日：2017-10-24
申请号：US15333505
申请日：2016-10-25
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Zhaoyin D. Wu , Christopher J. Borrelli , Geoffrey Zhang
CPC classification number: H04L25/03885 , G01R31/02 , G01R31/44 , H04L7/0025 , H04L7/0087 , H04L25/03273
Abstract: An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.
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公开(公告)号：US09654327B2
公开(公告)日：2017-05-16
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
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公开(公告)号：US09313017B1
公开(公告)日：2016-04-12
申请号：US14737330
申请日：2015-06-11
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Zhaoyin D. Wu , Kun-Yung Chang
CPC classification number: H04L7/0087 , H04L7/0025 , H04L7/0062 , H04L25/03
Abstract: In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.
Abstract translation: 在一个示例中，用于接收机的时钟数据恢复（CDR）电路包括定时误差检测器电路，环路滤波器和相位内插器。 定时误差检测器电路被耦合以以波特率接收由接收器接收的符号的数据样本和误差样本。 定时误差检测器电路可操作以基于数据样本和误差样本同时产生每个符号的定时误差值和估计波形值。 环路滤波器耦合到定时误差检测器以接收定时误差值。 相位内插器耦合到环路滤波器以接收滤波的定时误差值，相位插值器可操作以产生控制信号以调整用于生成数据样本和误差采样的采样相位。
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公开(公告)号：US09237047B1
公开(公告)日：2016-01-12
申请号：US14689294
申请日：2015-04-17
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Patrick Satarzadeh , Zhaoyin D. Wu
CPC classification number: H04L27/06 , H04L25/061
Abstract: A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit coupled to receive the input signal; and a calibration circuit coupled to the receiver, the calibration circuit having an input for receiving the input signal; an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.
Abstract translation: 描述了用于在集成电路中接收数据的电路。 该电路包括接收器，配置为接收输入信号并基于输入信号产生输出数据，接收器具有耦合以接收输入信号的电平检测电路; 以及校准电路，其耦合到所述接收器，所述校准电路具有用于接收所述输入信号的输入; 耦合到所述输入端的误差检测电路，所述误差检测电路被耦合以接收所述输入信号，第一参考电压和第二参考电压; 以及耦合到所述误差检测电路的输出的控制电路，其中所述控制电路基于所述输入信号与所述第一参考电压和所述第二参考电压的比较来选择性地产生偏移控制信号或幅度控制信号。 还公开了接收数据的方法。
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公开(公告)号：US20150145615A1
公开(公告)日：2015-05-28
申请号：US14092241
申请日：2013-11-27
Applicant: Xilinx, Inc.
Inventor： Jing Jing , Shuxian Wu , Zhaoyin D. Wu
CPC classification number: H03H7/0115 , H01L23/5223 , H01L23/5227 , H01L27/016 , H01L28/10 , H01L28/60 , H01L28/88 , H01L2924/0002 , H03H5/02 , H03H7/0138 , H05K1/16 , Y10T29/49117 , H01L2924/00
Abstract: A circuit includes a first finger capacitor having a first bus line coupled to a first plurality of finger elements and a second bus line coupled to a second plurality of finger elements. The first bus line is parallel to the second bus line. The circuit further includes an inductor having a first leg oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center of the first bus line.
Abstract translation: 电路包括具有耦合到第一多个指状元件的第一总线和耦合到第二多个指状元件的第二总线的第一指状电容器。 第一条总线与第二条总线平行。 电路还包括具有垂直于第一总线线路和第二总线线路定向的第一支路的电感器。 电感器的第一段耦合到第一总线的中心。
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