公开(公告)号：US10715702B1

公开(公告)日：2020-07-14

申请号：US16351158

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Christopher H. Dick ,  Xiaohan Chen ,  Hemang M. Parekh

IPC: H04L25/49 ,  H04L25/03 ,  H04N5/21 ,  H03F1/32 ,  H04N5/00

Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some examples, a non-linear datapath is coupled to the input, where the non-linear datapath is configured to add a non-linear mirror image component to the DPD input signal to provide a non-linear signal that is used to generate a first predistortion signal. In some embodiments, a linear datapath is coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. A first combiner is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

公开(公告)号：US20200089472A1

公开(公告)日：2020-03-19

申请号：US16136041

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC: G06F7/499 ,  G06F7/544 ,  G06F9/38 ,  G06F9/30

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

公开(公告)号：US20190303033A1

公开(公告)日：2019-10-03

申请号：US15944160

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Tim Tuan ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick

IPC: G06F3/06

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

公开(公告)号：US09787289B2

公开(公告)日：2017-10-10

申请号：US14791811

申请日：2015-07-06

Applicant: Xilinx, Inc.

Inventor： Fredric J. Harris ,  Christopher H. Dick

IPC: H03H7/46 ,  H03H17/02

CPC classification number: H03H17/0266

Abstract: Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information therefrom and configured for generating inner filtered samples of the information obtained from the path. The inner filtered samples are for moving an edge of a passband associated with the outer filtered samples toward a center of the passband.

公开(公告)号：US20140133527A1

公开(公告)日：2014-05-15

申请号：US13674867

申请日：2012-11-12

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick

IPC: H04B7/005

CPC classification number: H04B7/005 ,  H03F1/3247 ,  H03F3/189 ,  H03F3/245 ,  H03F2201/3212 ,  H03F2201/3233

Abstract: A method of performing digital pre-distortion in a communication network is described. The method comprises implementing a transceiver in the communication network, the transceiver enabling the transfer of communication signals in the communication network by way of a wireless communication channel; sampling signals, at the transceiver, associated with a transmit signal which are necessary to perform digital pre-distortion; providing the sampled signals to a remote computer; and generating, at the remote computer, parameters to be applied to a digital pre-distortion circuit of the transceiver. A communication network configured to enable digital pre-distortion is also described.

Abstract translation: 描述了在通信网络中执行数字预失真的方法。 该方法包括在通信网络中实现收发信机，收发机能够通过无线通信信道传送通信网络中的通信信号; 在收发器处采样信号与执行数字预失真所必需的发射信号相关联; 将采样信号提供给远程计算机; 以及在所述远程计算机处产生要应用于所述收发器的数字预失真电路的参数。 还描述了被配置为实现数字预失真的通信网络。

公开(公告)号：US11704536B1

公开(公告)日：2023-07-18

申请号：US16427214

申请日：2019-05-30

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Christopher H. Dick

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/08

Abstract: Disclosed approaches for convolving input feature maps in a neural network include a circuit arrangement circuit that includes memory circuitry and convolution circuitry. The memory circuitry is configured to store K NxN first filters, and C 1x1 second filters, wherein N ≥ 1, and 1

公开(公告)号：US10747690B2

公开(公告)日：2020-08-18

申请号：US15944307

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H K Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  H04L12/933

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

公开(公告)号：US20190303311A1

公开(公告)日：2019-10-03

申请号：US15944307

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran HK Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/16 ,  G06F13/40

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

公开(公告)号：US10411656B1

公开(公告)日：2019-09-10

申请号：US16142893

申请日：2018-09-26

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick ,  Hongzhi Zhao ,  Hemang M. Parekh ,  Xiaohan Chen

IPC: H03F1/32 ,  H04L27/26 ,  H04B1/04 ,  H04N5/38 ,  H04L27/08

Abstract: A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

公开(公告)号：US20170005627A1

公开(公告)日：2017-01-05

申请号：US14790364

申请日：2015-07-02

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Christopher H. Dick

IPC: H03F1/32 ,  H03F3/24 ,  H04B1/04 ,  H03F3/189

CPC classification number: H03F1/3247 ,  H03F1/3252 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/195 ,  H03F3/24 ,  H03F3/245 ,  H03F2201/3209 ,  H03F2201/3215 ,  H03F2201/3224 ,  H03F2201/3233 ,  H04B1/0475 ,  H04B2001/0425

Abstract: An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. A combiner is for combining the first predistorted signal and the second predistorted signal for providing an output signal. The first digital predistortion module includes a moving mean block for receiving the input signal for providing a moving mean signal. The first digital predistortion module further includes a digital predistorter for receiving the input signal and the moving mean signal for providing the first predistorted signal.

Abstract translation: 装置一般涉及预处理输入信号。 在该装置中，第一数字预失真模块和第二数字预失真模块用于接收用于分别提供第一预失真信号和第二预失真信号的输入信号。 组合器用于组合第一预失真信号和第二预失真信号以提供输出信号。 第一数字预失真模块包括移动平均块，用于接收用于提供移动平均信号的输入信号。 第一数字预失真模块还包括用于接收输入信号的数字预失真器和用于提供第一预失真信号的移动平均信号。