公开(公告)号：US11416659B1

公开(公告)日：2022-08-16

申请号：US16834797

申请日：2020-03-30

申请人： Xilinx, Inc.

发明人： Pradip Kar ,  Nithin Kumar Guggilla ,  Bing Tian

IPC分类号： G06F30/31 ,  G06F12/02 ,  G06F30/39 ,  G06F30/398 ,  G06F30/392

摘要： Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

公开(公告)号：US10963460B2

公开(公告)日：2021-03-30

申请号：US16212134

申请日：2018-12-06

申请人： Xilinx, Inc.

发明人： Hare K. Verma ,  Bing Tian

IPC分类号： G06F16/00 ,  G06F16/2453 ,  G06F16/2455 ,  G06F9/30

摘要： Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.

公开(公告)号：US20200089472A1

公开(公告)日：2020-03-19

申请号：US16136041

申请日：2018-09-19

申请人： Xilinx, Inc.

发明人： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC分类号： G06F7/499 ,  G06F7/544 ,  G06F9/38 ,  G06F9/30

摘要： Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

公开(公告)号：US09268891B1

公开(公告)日：2016-02-23

申请号：US14535267

申请日：2014-11-06

申请人： Xilinx, Inc.

发明人： Krishna Garlapati ,  Elliott Delaye ,  Ashish Sirasao ,  Bing Tian

IPC分类号： G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC分类号： G06F17/5045 ,  G01R31/31703 ,  G01R31/3177

摘要： Compiling a circuit design includes receiving the circuit design specified in a hardware description language, detecting, using a processor, a slice of a vector within the circuit design, and determining that the slice is defined by a left slice boundary variable and a right slice boundary variable. A hardware description is generated from the circuit design using the processor by including a first shifter circuit receiving the left slice boundary variable as an input signal, a second shifter circuit receiving the right slice boundary variable as an input signal, a control signal generator coupled to the first and second shifter circuits, and an output stage. The output stage, responsive to a control signal dependent upon an output from the first shifter circuit and an output from second shifter circuit, generates an output signal including newly received values from a data signal only for bit locations of the output signal corresponding to the slice.

摘要翻译： 编译电路设计包括接收以硬件描述语言指定的电路设计，使用处理器检测电路设计内的向量片，以及确定该片由左片边界变量和右片段边界定义 变量。 通过包括接收左边界边界变量的第一移位器电路作为输入信号，接收右边界边界变量的第二移位器电路作为输入信号，通过使用处理器的电路设计产生硬件描述，控制信号发生器耦合到 第一和第二移位器电路以及输出级。 响应于取决于第一移位器电路的输出的控制信号和来自第二移位器电路的输出的输出级产生包括仅针对对应于切片的输出信号的位位置的来自数据信号的新接收值的输出信号 。

公开(公告)号：US10678983B1

公开(公告)日：2020-06-09

申请号：US15987372

申请日：2018-05-23

申请人： Xilinx, Inc.

发明人： Shangzhi Sun ,  Chaithanya Dudha ,  Bing Tian ,  Ashish Sirasao

IPC分类号： G06F30/3312 ,  G06F30/30 ,  G06F111/20 ,  G06F119/12

摘要： Local retiming for a circuit design includes determining, using computer hardware, a load of a synchronous circuit element within the circuit design tagged for forward retiming, traversing, using the computer hardware, each input of the load backward through the circuit design until a sequential circuit element or a primary input is reached, and adding, using the computer hardware, each synchronous circuit element encountered in the traversing to a forward retiming list. In response to determining that forward retiming criteria is met for the forward retiming list, the computer hardware modifies the circuit design by creating a new synchronous circuit element at an output of the load.

公开(公告)号：US09460253B1

公开(公告)日：2016-10-04

申请号：US14482945

申请日：2014-09-10

申请人： Xilinx, Inc.

发明人： Elliott Delaye ,  Ashish Sirasao ,  Krishna Garlapati ,  Bing Tian

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/64 ,  G06F2217/66

摘要： In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.

摘要翻译： 在一个示例中，一种处理电路设计的方法包括：在具有设计对象层级的电路设计的描述中确定第一分区，第一分区包括设计对象层级中的至少一个设计对象; 生成第一分区的签名; 用第一分区的签名查询数据库以识别第一分区的多个预定义的实现; 以及基于用于所述第一分区的所述多个预定义实现的所选择的预定义实现来生成用于目标集成电路（IC）的电路设计的实现。

公开(公告)号：US10726175B1

公开(公告)日：2020-07-28

申请号：US16291952

申请日：2019-03-04

申请人： Xilinx, Inc.

发明人： Chaithanya Dudha ,  Satyaprakash Pareek ,  Bing Tian ,  Ashish Sirasao

IPC分类号： G06F30/30 ,  H01L27/02 ,  G06F30/327 ,  G06F30/398 ,  G06F30/00

摘要： A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

公开(公告)号：US20200183937A1

公开(公告)日：2020-06-11

申请号：US16212134

申请日：2018-12-06

申请人： Xilinx, Inc.

发明人： Hare K. Verma ,  Bing Tian

IPC分类号： G06F16/2453 ,  G06F16/2455 ,  G06F9/30

摘要： Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.

公开(公告)号：US10664561B1

公开(公告)日：2020-05-26

申请号：US15729483

申请日：2017-10-10

申请人： Xilinx, Inc.

发明人： Pradip K. Kar ,  Satyaprakash Pareek ,  Shangzhi Sun ,  Bing Tian

IPC分类号： G06F17/50

摘要： Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.

公开(公告)号：US10606979B1

公开(公告)日：2020-03-31

申请号：US16001206

申请日：2018-06-06

申请人： Xilinx, Inc.

发明人： Shangzhi Sun ,  Bing Tian ,  Chaithanya Dudha

IPC分类号： G06F17/50

摘要： Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.