公开(公告)号：US20190114533A1

公开(公告)日：2019-04-18

申请号：US15785679

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Sonal Santan ,  Soren T. Soe ,  Ashish Sirasao ,  Ehsan Ghasemi ,  Sean Settle

IPC: G06N3/063 ,  G06N3/10 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.

公开(公告)号：US11222256B2

公开(公告)日：2022-01-11

申请号：US15785685

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Xiao Teng ,  Aaron Ng ,  Ashish Sirasao ,  Elliott Delaye

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: At least one neural network accelerator performs operations of a first subset of layers of a neural network on an input data set, generates an intermediate data set, and stores the intermediate data set in a shared memory queue in a shared memory. A first processor element of a host computer system provides input data to the neural network accelerator and signals the neural network accelerator to perform the operations of the first subset of layers of the neural network on the input data set. A second processor element of the host computer system reads the intermediate data set from the shared memory queue, performs operations of a second subset of layers of the neural network on the intermediate data set, and generates an output data set while the neural network accelerator is performing the operations of the first subset of layers of the neural network on another input data set.

公开(公告)号：US10678509B1

公开(公告)日：2020-06-09

申请号：US16106743

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Sean Settle ,  Elliott Delaye ,  Aaron Ng ,  Ehsan Ghasemi ,  Ashish Sirasao ,  Xiao Teng ,  Jindrich Zejda

IPC: G06F7/544 ,  G06F7/533 ,  G06N3/08 ,  G06N3/04

Abstract: An example multiply accumulate (MACC) circuit includes a multiply-accumulator having an accumulator output register, a scaler, coupled to the multiply accumulator, and a control circuit coupled to the multiply-accumulator and the scaler. The control circuit is configured to provide control data to the scaler, the control data indicative of: a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register for implementing a first right shift; a multiplier; and a second right shift.

公开(公告)号：US10572225B1

公开(公告)日：2020-02-25

申请号：US16142406

申请日：2018-09-26

Applicant: Xilinx, Inc.

Inventor： Ehsan Ghasemi ,  Elliott Delaye ,  Ashish Sirasao ,  Sean Settle

IPC: G06F7/544 ,  G06N3/02 ,  G06T1/60 ,  G06N3/08

Abstract: A and a request generator circuit is configured to read data elements of a three-dimensional (3-D) input feature map (IFM) from a memory and store a subset of the data elements in one of a plurality of N line buffers. Each line buffer is configured for storage of M data elements. A pixel iterator circuit is coupled to the line buffers and is configured to generate a sequence of addresses for reading the stored data elements from the line buffers based on a sequence of IFM height values and a sequence of IFM width values.

公开(公告)号：US10460416B1

公开(公告)日：2019-10-29

申请号：US15786244

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Ashish Sirasao ,  Elliott Delaye ,  Aaron Ng ,  Ehsan Ghasemi

IPC: G06T1/20 ,  G06T1/60 ,  H04N21/2381 ,  G06F3/03 ,  H03K19/177 ,  H04N5/30 ,  G06F12/00

Abstract: An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a plurality of memory banks configured to store the image data; multiplexer circuitry coupled to the memory banks; a first plurality of registers coupled to the multiplexer circuitry; a second plurality of registers coupled to the first plurality of registers, outputs of the second plurality of registers configured to provide the plurality of streams of image samples; and control circuitry configured to generate addresses for the plurality of memory banks, control the multiplexer circuitry to select among outputs of the plurality of memory banks, control the first plurality of registers to store outputs of the second plurality of multiplexers, and control the second plurality of registers to store outputs of the first plurality of registers.

公开(公告)号：US10411709B1

公开(公告)日：2019-09-10

申请号：US16045657

申请日：2018-07-25

Applicant: Xilinx, Inc.

Inventor： Ehsan Ghasemi ,  Elliott Delaye ,  Ashish Sirasao

IPC: H03K19/173 ,  G06F17/50 ,  H03K19/177 ,  G06F12/0802

Abstract: Disclosed circuits and methods include N line buffers. Each line buffer is configured for storage of M data elements of a three-dimensional (3-D) input feature map (IFM). A request generator circuit is coupled to the N line buffers and to a memory configured for storage of the 3-D IFM. The request generator circuit is divides the 3-D IFM into a plurality of IFM sub-volumes based on values of N, M, and dimensions of the 3-D IFM. The request generator circuit reads from the memory, data elements at addresses of an unprocessed one of the IFM sub-volumes and stores the data elements of the unprocessed one of the IFM sub-volumes in the N line buffers. In response to a completion signal, the request generator circuit repeats the reading of an unprocessed one of the IFM sub-volumes and storing the data elements in the N line buffers.

公开(公告)号：US10354733B1

公开(公告)日：2019-07-16

申请号：US15786321

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Elliott Delaye ,  Ashish Sirasao ,  Yongjun Wu ,  Aaron Ng

IPC: G11C8/00 ,  G11C16/10 ,  G06N3/04 ,  G06F12/06 ,  G06F13/16 ,  G06N20/00

Abstract: Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.

公开(公告)号：US10303833B1

公开(公告)日：2019-05-28

申请号：US15429014

申请日：2017-02-09

Applicant: Xilinx, Inc.

Inventor： Aman Gayasen ,  Surya Pratik Saha ,  Elliott Delaye ,  Shangzhi Sun ,  Ashish Sirasao

IPC: G06F17/50

Abstract: Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.

公开(公告)号：US09460253B1

公开(公告)日：2016-10-04

申请号：US14482945

申请日：2014-09-10

Applicant: Xilinx, Inc.

Inventor： Elliott Delaye ,  Ashish Sirasao ,  Krishna Garlapati ,  Bing Tian

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/64 ,  G06F2217/66

Abstract: In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.

Abstract translation: 在一个示例中，一种处理电路设计的方法包括：在具有设计对象层级的电路设计的描述中确定第一分区，第一分区包括设计对象层级中的至少一个设计对象; 生成第一分区的签名; 用第一分区的签名查询数据库以识别第一分区的多个预定义的实现; 以及基于用于所述第一分区的所述多个预定义实现的所选择的预定义实现来生成用于目标集成电路（IC）的电路设计的实现。

公开(公告)号：US08938700B1

公开(公告)日：2015-01-20

申请号：US13762251

申请日：2013-02-07

Applicant: Xilinx, Inc.

Inventor： Elliott Delaye ,  Alireza S. Kaviani ,  Ashish Sirasao ,  Yinyi Wang

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Data-driven processing of a circuit design includes converting each pattern of one or more input patterns from a first format into a second format. Each pattern identifies one or more inputs and one or more outputs and specifies each function that generates each of the one or more outputs from the one or more inputs. Each pattern of the second format is stored in a database. An input circuit design is searched for circuit design elements that match patterns in the database. Data indicative of each pattern in the database that matches a circuit design element is output.

Abstract translation: 电路设计的数据驱动处理包括将一个或多个输入模式的每个模式从第一格式转换为第二格式。 每个模式识别一个或多个输入和一个或多个输出，并且指定从一个或多个输入产生一个或多个输出中的每一个的每个功能。 第二格式的每个模式都存储在数据库中。 搜索与数据库中的模式匹配的电路设计元素的输入电路设计。 输出指示数据库中与电路设计元素匹配的每个模式的数据。