知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.02 秒)

    Multi-port stream switch for stream interconnect network
    3.
    发明授权
    Multi-port stream switch for stream interconnect network 有权

    公开(公告)号：US11323391B1

    公开(公告)日：2022-05-03

    申请号：US16833029

    申请日：2020-03-27

    申请人： XILINX, INC.

    发明人： Peter McColgan ,  David Clarke ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Tim Tuan

    IPC分类号： H04L12/935 ,  G06F13/28 ,  H04L49/00

    摘要： Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.

    LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH MULTIPLE PROCESSOR CORES
    6.
    发明申请
    LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH MULTIPLE PROCESSOR CORES 有权

    公开(公告)号：US20230044581A1

    公开(公告)日：2023-02-09

    申请号：US17394714

    申请日：2021-08-05

    申请人： Xilinx, Inc.

    发明人： Tim Tuan ,  Seokjoong Kim ,  Sai Anirudh Jayanthi

    IPC分类号： G06F30/20 ,  G06F1/06 ,  G06F1/28 ,  G06F12/02

    摘要： Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.

    Multi-die integrated circuit with data processing engine array
    8.
    发明授权
    Multi-die integrated circuit with data processing engine array 有权

    公开(公告)号：US11288222B1

    公开(公告)日：2022-03-29

    申请号：US17035368

    申请日：2020-09-28

    申请人： Xilinx, Inc.

    发明人： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

    IPC分类号： G06F13/40 ,  G06F13/16

    摘要： A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

    Multi-die integrated circuit with data processing engine array
    9.
    发明授权
    Multi-die integrated circuit with data processing engine array 有权

    公开(公告)号：US12001367B2

    公开(公告)日：2024-06-04

    申请号：US18320147

    申请日：2023-05-18

    申请人： Xilinx, Inc.

    发明人： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

    IPC分类号： G06F13/40 ,  G06F13/16

    CPC分类号： G06F13/4027 ,  G06F13/1668

    摘要： An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.