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    CIRCUITS FOR AND METHODS OF CONTROLLING THE OPERATION OF A HYBRID MEMORY SYSTEM
    2.
    发明申请
    CIRCUITS FOR AND METHODS OF CONTROLLING THE OPERATION OF A HYBRID MEMORY SYSTEM 有权
    用于控制混合存储器系统的操作的电路和方法

    公开(公告)号：US20160217835A1

    公开(公告)日：2016-07-28

    申请号：US14607978

    申请日：2015-01-28

    Applicant: Xilinx, Inc.

    Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

    IPC: G11C7/10 ,  G06F12/02 ,  G06F12/08

    CPC classification number: G11C7/1057 ,  G06F12/0246 ,  G06F12/0813 ,  G06F13/1694 ,  G06F2212/7203 ,  G11C7/1072

    Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

    Abstract translation: 描述用于控制具有不同类型的存储器的存储器系统的操作的电路。 该电路包括具有第一类型的存储元件并且具有第一存取时间的第一存储器; 具有第二类型的存储元件并具有第二存取时间的第二存储器，其中所述第二类型的存储元件不同于所述第一类型的存储元件; 存储器控制电路，其能够访问第一存储器和第二存储器; 延迟缓冲器，其耦合到所述第二存储器，以补偿所述第一访问时间和所述第二访问时间的差异; 以及用于合并第一存储器的输出和第二存储器的延迟输出的电路，以产生有序的输出数据。 还公开了一种控制存储器系统的操作的方法。

    AXI-CAPI adapter
    4.
    发明授权
    AXI-CAPI adapter 有权

    公开(公告)号：US10482054B1

    公开(公告)日：2019-11-19

    申请号：US15261626

    申请日：2016-09-09

    Applicant: Xilinx, Inc.

    Inventor： Ling Liu ,  Michaela Blott ,  Kimon Karras ,  Thomas Janson ,  Kornelis A. Vissers

    IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L12/861

    Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

    Implementation-tuned architecture for neural network processing in a learned transform domain
    6.
    发明授权
    Implementation-tuned architecture for neural network processing in a learned transform domain 有权

    公开(公告)号：US12271818B1

    公开(公告)日：2025-04-08

    申请号：US17330048

    申请日：2021-05-25

    Applicant: XILINX, INC.

    Inventor： Kristof Denolf ,  Alireza Khodamoradi ,  Kornelis A. Vissers

    IPC: G06N3/08 ,  G06N3/04 ,  G06N3/082

    Abstract: Embodiments herein describe a learnable transform block disposed before, or in between, the neural network layers to transform received data into a more computational-friendly domain while preserving discriminative features required for the neural network to generate accurate results. In one embodiment, during a training phase, an AI system learns parameters for the transform block that are then used during the inference phase to transform received data into the computational-friendly domain that has a reduced size input. The transformed data may require less compute resources or less memory usage to process by the underlying hardware device that hosts the neural network.

    Error aware module redundancy for machine learning
    7.
    发明授权
    Error aware module redundancy for machine learning 有权

    公开(公告)号：US11934932B1

    公开(公告)日：2024-03-19

    申请号：US17094598

    申请日：2020-11-10

    Applicant: XILINX, INC.

    Inventor： Giulio Gambardella ,  Nicholas Fraser ,  Ussama Zahid ,  Michaela Blott ,  Kornelis A. Vissers

    IPC: G06N20/20 ,  G06F11/16 ,  G06N3/045 ,  G06N3/08

    CPC classification number: G06N20/20 ,  G06F11/16 ,  G06N3/045 ,  G06N3/08

    Abstract: Examples herein propose operating redundant ML models which have been trained using a boosting technique that considers hardware faults. The embodiments herein describe performing an evaluation process where the performance of a first ML model is measured in the presence of a hardware fault. The errors introduced by the hardware fault can then be used to train a second ML model. In one embodiment, a second evaluation process is performed where the combined performance of both the first and second trained ML models is measured in the presence of a hardware fault. The resulting errors can then be used when training a third ML model. In this manner, the three trained ML models are trained to be error aware. As a result, during operation, if a hardware fault occurs, the three ML models have better performance relative to three ML models that where not trained to be error aware.

    Data mover circuitry for N-dimensional data in an integrated circuit
    8.
    发明授权
    Data mover circuitry for N-dimensional data in an integrated circuit 有权

    公开(公告)号：US11327677B1

    公开(公告)日：2022-05-10

    申请号：US17019454

    申请日：2020-09-14

    Applicant: Xilinx, Inc.

    Inventor： Kristof Denolf ,  Jack S. Lo ,  Kornelis A. Vissers

    IPC: G06F3/06

    Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.

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