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公开(公告)号：US10411656B1
公开(公告)日：2019-09-10
申请号：US16142893
申请日：2018-09-26
Applicant: Xilinx, Inc.
Inventor： Christopher H. Dick , Hongzhi Zhao , Hemang M. Parekh , Xiaohan Chen
Abstract: A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.
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2.发明授权公开(公告)号：US11942904B2
公开(公告)日：2024-03-26
申请号：US17402892
申请日：2021-08-16
Applicant: Xilinx, Inc.
Inventor： Hongzhi Zhao , Xing Zhao , Vincent C. Barnes , Xiaohan Chen , Hemang M. Parekh
CPC classification number: H03F1/3247 , H03F3/21 , H03G1/0005 , H03F2201/3227
Abstract: A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.
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公开(公告)号：US20200099416A1
公开(公告)日：2020-03-26
申请号：US16142295
申请日：2018-09-26
Applicant: Xilinx, Inc.
Inventor： Christopher H. Dick , Hongzhi Zhao , Hemang M. Parekh , Xiaohan Chen
Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, a non-linear datapath is coupled to the input, where the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input. By way of example, each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to a non-linear component of an amplifier. In various examples, a first combiner combines an output of each of the plurality of datapath elements to generate a first predistortion signal. In some embodiments, the DPD system further includes a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In addition, a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal.
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公开(公告)号：US09866269B1
公开(公告)日：2018-01-09
申请号：US15354858
申请日：2016-11-17
Applicant: Xilinx, Inc.
Inventor： Hongzhi Zhao , Christopher H. Dick , Hemang M. Parekh
CPC classification number: H04B1/62 , H03F1/3247 , H03F1/3252 , H03F1/3258 , H03F3/195 , H03F3/245 , H03F2201/3209 , H03F2201/3224 , H03F2201/3233 , H04L25/03847
Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. The DPD system includes a first predistortion circuit configured to provide a first signal path coupled to the input to generate a first predistortion signal. The first predistortion circuit includes a first infinite impulse response (IIR) filter. A second predistortion circuit is configured to provide a second signal path coupled to the input in parallel with the first signal path to generate a second predistortion signal. The second predistortion circuit includes a second IIR filter. A combiner circuit is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.
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公开(公告)号：US10944444B2
公开(公告)日：2021-03-09
申请号：US16142295
申请日：2018-09-26
Applicant: Xilinx, Inc.
Inventor： Christopher H. Dick , Hongzhi Zhao , Hemang M. Parekh , Xiaohan Chen
Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, a non-linear datapath is coupled to the input, where the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input. By way of example, each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to a non-linear component of an amplifier. In various examples, a first combiner combines an output of each of the plurality of datapath elements to generate a first predistortion signal. In some embodiments, the DPD system further includes a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In addition, a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal.
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Patent Agency Ranking
公开(公告)号：US10715702B1
公开(公告)日：2020-07-14
申请号：US16351158
申请日：2019-03-12
Applicant: Xilinx, Inc.
Inventor： Hongzhi Zhao , Christopher H. Dick , Xiaohan Chen , Hemang M. Parekh
Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some examples, a non-linear datapath is coupled to the input, where the non-linear datapath is configured to add a non-linear mirror image component to the DPD input signal to provide a non-linear signal that is used to generate a first predistortion signal. In some embodiments, a linear datapath is coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. A first combiner is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.
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公开(公告)号：US11984919B2
公开(公告)日：2024-05-14
申请号：US17959079
申请日：2022-10-03
Applicant: XILINX, INC.
Inventor： Hongzhi Zhao , Christophe Erdmann , Hemang M. Parekh , Xing Zhao , Xiaohan Chen
Abstract: Embodiments herein describe a PIM correction circuit. In a base station, TX and RX RF changes, band pass filters, duplexers, and diplexers can have severe memory effects due to their sharp transition bandwidth from pass band to stop band. PIM interference, generated by the TX signals and reflected onto the RX RF chain will include these memory effects. These memory effects make PIM cancellation complex, requiring complicated computations and circuits. However, the embodiments herein use a PIM correction circuit that separates the memory effects of the TX and RX paths from the memory effects of PIM, thereby reducing PIM cancellation complexity and hardware implementation cost.
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8.发明申请公开(公告)号：US20230046588A1
公开(公告)日：2023-02-16
申请号：US17402892
申请日：2021-08-16
Applicant: Xilinx, Inc.
Inventor： Hongzhi Zhao , Xing Zhao , Vincent C. Barnes , Xiaohan Chen , Hemang M. Parekh
Abstract: A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.
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公开(公告)号：US11563453B1
公开(公告)日：2023-01-24
申请号：US17239395
申请日：2021-04-23
Applicant: XILINX, INC.
Inventor： Hongzhi Zhao , Vincent C. Barnes , Xiaohan Chen , Hemang M. Parekh
Abstract: A transmitter for a communication system comprises a digital pre-distortion (DPD) circuit and adaptation circuitry. The DPD circuit is configured to generate a digital intermediate signal by compensating an input signal for distortions resulting from an amplifier. The amplifier is configured to output an output signal based on the digital intermediate signal. The DPD circuit includes one or more an infinite impulse response (IIR) filters configured to implement a first transfer function based on a first parameter, and a second transfer function based on the first parameter and a time constant. The DPD circuit is configured to generate an adjustment signal based on the first transfer function and the second transfer function. The adaptation circuitry is configured to update the first parameter based on the adjustment signal, the input signal, and the output signal.
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公开(公告)号：US11483018B1
公开(公告)日：2022-10-25
申请号：US17339241
申请日：2021-06-04
Applicant: XILINX, INC.
Inventor： Xiaohan Chen , Hemang M. Parekh , John Edward McGrath , Hongzhi Zhao , David Eugene Melinn
IPC: H04B1/04
Abstract: Examples described herein provide a radio frequency circuit. The radio frequency circuit includes a controller; a parameter estimator circuit; a capture circuit; and a pre-distorter circuit. The pre-distorter generally includes one or more nonlinear filter circuits and configurable hardware circuitry. Each of the one or more the nonlinear filter circuits includes: adder(s); multiplier(s); and memories coupled to at least one of the adder(s) and the multiplier(s); where the configurable hardware circuitry is configured to distort one or more input signals by directing the one or more input signals along a path through the one or more adders, the one or more multipliers, and the one or more memories and by distorting the one or input signals using the nonlinear parameters stored in the one or more memories as the one or more input signals travels the path.
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