公开(公告)号：US20170053980A1

公开(公告)日：2017-02-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.

Abstract translation: 制造单个扩散断裂的方法包括：提供具有与鳍片交叉的两个栅极结构的翅片和与鳍片交叉的中间伪栅极结构，其中中间伪栅极结构被栅极结构夹持。 之后，形成多个间隔物，并且每个间隔物分别围绕栅极结构和中间虚拟栅极结构。 然后，将中间的虚拟栅极结构和直接位于中间的虚拟栅极结构下面的鳍的一部分去除以形成凹部。 最后，形成凹部中的隔离层以封闭凹部的入口，以便形成嵌入凹槽内的空隙。

公开(公告)号：US10573649B2

公开(公告)日：2020-02-25

申请号：US15045258

申请日：2016-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Chia-Hsun Tseng ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L27/092 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/737

Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

公开(公告)号：US09653345B1

公开(公告)日：2017-05-16

申请号：US14989802

申请日：2016-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shang-Nan Chou ,  Che-Yi Lin ,  En-Chiuan Liou ,  Yu-Ting Hung ,  Shin-Feng Su ,  Chia-Hsun Tseng

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L21/76802 ,  H01L21/0276 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832

Abstract: A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.

公开(公告)号：US20170115579A1

公开(公告)日：2017-04-27

申请号：US15260322

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Yi-Jing Wang ,  Chia-Hsun Tseng

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  H01L21/02642 ,  H01L21/027 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.

公开(公告)号：US20170025286A1

公开(公告)日：2017-01-26

申请号：US14809270

申请日：2015-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Te Chen ,  Chia-Hsun Tseng ,  En-Chiuan Liou ,  Chiung-Lin Hsu ,  Meng-Lin Tsai ,  Jan-Fu Yang ,  Yu-Ting Hung ,  Shin-Feng Su

IPC: H01L21/321 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/225

CPC classification number: H01L21/2253 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821

Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.

Abstract translation: 调整半导体器件的沟道宽度的方法包括提供分成第一区域和第二区域的衬底，其中衬底包括多个鳍片。 在第一区域内的翅片上执行第一注入工艺。 然后，对第二区域内的翅片执行第二注入工艺，其中第一注入工艺和第二注入工艺在包括掺杂剂种类，掺杂剂剂量或注入能量的至少一个条件中彼此不同。 之后，同时去除第一区域和第二区域内的部分散热片，以在第一区域内形成多个第一凹槽，在第二区域内形成多个第二凹槽。 最后，形成第一外延层和第二外延层以分别填充每个第一凹槽和每个第二凹槽。

公开(公告)号：US09543203B1

公开(公告)日：2017-01-10

申请号：US14791242

申请日：2015-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Wei-Hao Huang ,  Yu-Ting Hung

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

Abstract translation: 制造半导体结构的方法包括以下步骤：在衬底上形成第一层间电介质; 在所述基板上形成栅电极，使得所述栅电极的周围被所述第一层间电介质包围; 在所述栅电极上形成至少包含一层有机材料的图案化掩模层; 形成保形绝缘层以保形地覆盖有机材料层; 以及形成覆盖所述共形介电层的第二层间电介质。

公开(公告)号：US20170004997A1

公开(公告)日：2017-01-05

申请号：US14791242

申请日：2015-07-02

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Wei-Hao Huang ,  Yu-Ting Hung

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

Abstract translation: 制造半导体结构的方法包括以下步骤：在衬底上形成第一层间电介质; 在所述基板上形成栅电极，使得所述栅电极的周围被所述第一层间电介质包围; 在所述栅电极上形成至少包含一层有机材料的图案化掩模层; 形成保形绝缘层以保形地覆盖有机材料层; 以及形成覆盖所述共形介电层的第二层间电介质。

公开(公告)号：US20160126139A1

公开(公告)日：2016-05-05

申请号：US14557387

申请日：2014-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Chia-Hsun Tseng

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/02186 ,  H01L21/02244 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有高k电介质层的衬底; 在高k电介质层上形成第一功函数层; 以及在所述第一功函数层上形成第一含氧层。

公开(公告)号：US09711358B2

公开(公告)日：2017-07-18

申请号：US15399715

申请日：2017-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Te Chen ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Shin-Feng Su ,  Yu-Ting Hung ,  Meng-Lin Tsai

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0275 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.

公开(公告)号：US09673040B2

公开(公告)日：2017-06-06

申请号：US14557387

申请日：2014-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Chia-Hsun Tseng

IPC: H01L21/70 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/02 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L21/02186 ,  H01L21/02244 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer.