公开(公告)号：US08283674B2

公开(公告)日：2012-10-09

申请号：US12158382

申请日：2006-10-26

Applicant: Takeyoshi Masuda ,  Shinji Matsukawa

Inventor： Takeyoshi Masuda ,  Shinji Matsukawa

IPC: H01L29/15

CPC classification number: C23C16/325 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/046 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66068 ,  H01L29/78

Abstract: MOSFET is provided with SiC film. SiC film has a facet on its surface, and the length of one period of the facet is 100 nm or more, and the facet is used as channel. Further, a manufacturing method of MOSFET includes: a step of forming SiC film; a heat treatment step of heat-treating SiC film in a state where Si is supplied on the surface of SiC film; and a step of forming the facet obtained on the surface of SiC film by the heat treatment step into a channel. Thereby, it is possible to sufficiently improve the characteristics.

Abstract translation: MOSFET提供有SiC膜。 SiC薄膜在其表面具有一个刻面，该刻面的一个周期的长度为100nm或更大，并且该刻面用作通道。 此外，MOSFET的制造方法包括：形成SiC膜的工序; 在Si膜的表面供给Si的状态下对SiC膜进行热处理的热处理工序; 以及通过热处理步骤将在SiC膜的表面上获得的刻面形成沟道的步骤。 由此，可以充分提高特性。

公开(公告)号：US20120235165A1

公开(公告)日：2012-09-20

申请号：US13512459

申请日：2010-12-17

Applicant: Shin Harada ,  Toru ` Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Toru ` Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda

IPC: H01L29/38 ,  H01L21/20

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/049 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/94

Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −° and not more than +5° relative to a (0-33-8) plane in a direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm−3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.

Abstract translation: 一种半导体器件包括：由碳化硅制成的衬底，其具有相对于（0-33-8）面在01-10°内具有不小于-0且不大于+ 5°的偏离角的主表面 方向; 由碳化硅制成的p型层，通过外延生长形成在衬底的主表面上; 以及形成为与p型层的表面接触的氧化物膜。 在p型层和氧化膜之间的界面10nm以内的区域中，氮原子浓度的最大值为1×1021cm-3以上。

公开(公告)号：US20120025208A1

公开(公告)日：2012-02-02

申请号：US13258907

申请日：2010-09-29

Applicant: Taro Nishiguchi ,  Takeyoshi Masuda ,  Makoto Sasaki ,  Shin Harada ,  Yasuo Namikawa ,  Shinsuke Fujiwara

Inventor： Taro Nishiguchi ,  Takeyoshi Masuda ,  Makoto Sasaki ,  Shin Harada ,  Yasuo Namikawa ,  Shinsuke Fujiwara

IPC: H01L29/161 ,  H01L21/762

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/0475 ,  H01L21/187 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; forming a Si film made of silicon on a main surface of the base substrate; fabricating a stacked substrate by placing the SiC substrate on and in contact with the Si film; and connecting the base substrate and the SiC substrate to each other by heating the stacked substrate to convert, into silicon carbide, at least a region making contact with the base substrate and a region making contact with the SiC substrate in the Si film.

Abstract translation: 制造碳化硅基板的方法包括以下步骤：制备由碳化硅制成的基底基板和由单晶碳化硅制成的SiC基板; 在所述基底基板的主表面上形成由硅制成的Si膜; 通过将SiC衬底置于Si膜上并与其接触来制造堆叠衬底; 并且通过加热所述堆叠的基板将所述基底基板和所述SiC基板彼此连接，以将至少与所述基底基板接触的区域和与所述Si膜中的所述SiC基板接触的区域转化为碳化硅。

公开(公告)号：US20110210342A1

公开(公告)日：2011-09-01

申请号：US13128438

申请日：2010-02-09

Applicant: Makoto Sasaki ,  Takeyoshi Masuda

Inventor： Makoto Sasaki ,  Takeyoshi Masuda

IPC: H01L29/02 ,  B26D1/00

CPC classification number: H01L29/7802 ,  C30B29/36 ,  H01L23/544 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10T83/04 ,  H01L2924/00

Abstract: A SiC substrate includes a first orientation flat parallel to the direction, and a second orientation flat being in a direction intersecting the first orientation flat and being different from the first orientation flat in length. An alternative SiC substrate has a rectangular plane shape, and a main surface of the substrate includes a first side parallel to the direction, a second side in a direction perpendicular to the first side, and a third side connecting the first side to the second side. A length of the third side projected in a direction in which the first side extends is different from a length of the third side projected in a direction in which the second side extends.

Abstract translation: SiC衬底包括平行于<11-20>方向的第一取向平板和与第一取向平面相交的方向并且与第一取向平面不同的第二取向平面。 替代的SiC衬底具有矩形平面形状，并且衬底的主表面包括平行于<11-20>方向的第一侧，在垂直于第一侧的方向上的第二侧和连接第一侧的第三侧 一边到第二边 沿第一侧延伸的方向突出的第三侧的长度不同于沿第二侧延伸的方向突出的第三侧的长度。

公开(公告)号：US20110180812A1

公开(公告)日：2011-07-28

申请号：US13121122

申请日：2010-05-12

Applicant: Takeyoshi Masuda ,  Misako Honaga

Inventor： Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/12 ,  H01L29/20

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66909 ,  H01L29/8083

Abstract: A MOSFET which is a semiconductor device capable of achieving a stable reverse breakdown voltage and reduced on-resistance includes a SiC wafer of an n conductivity type, a plurality of p bodies of a p conductivity type formed to include a first main surface of the SiC wafer, and n+ source regions of the n conductivity type formed in regions surrounded by the plurality of p bodies, respectively, when viewed two-dimensionally. Each of the p bodies has a circular shape when viewed two-dimensionally, and each of the n+ source regions is arranged concentrically with each of the p bodies and has a circular shape when viewed two-dimensionally. Each of the plurality of p bodies is arranged to be positioned at a vertex of a regular hexagon when viewed two-dimensionally.

Abstract translation: 作为能够实现稳定的反向击穿电压和降低的导通电阻的半导体器件的MOSFET包括n导电型的SiC晶片，形成为包括SiC晶片的第一主表面的多个p导电类型的多个p体 ，以及分别形成在由多个p体包围的区域中的n导电类型的n +源极区域。 每个p体在二维观察时具有圆形形状，并且n +源区域中的每一个与每个p体同心地布置，并且在二维观察时具有圆形形状。 当二维观察时，多个p体中的每一个被布置成定位在正六边形的顶点处。

公开(公告)号：US20110169016A1

公开(公告)日：2011-07-14

申请号：US13063298

申请日：2010-03-23

Applicant: Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

Inventor： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/316

CPC classification number: H01L29/7802 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/94

Abstract: A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.

Abstract translation: MOSFET包括：碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 MOSFET的子阈值斜率不超过0.4 V /十年。

公开(公告)号：US20100090259A1

公开(公告)日：2010-04-15

申请号：US12517761

申请日：2007-09-21

Applicant: Takeyoshi Masuda ,  Yasuo Namikawa

Inventor： Takeyoshi Masuda ,  Yasuo Namikawa

IPC: H01L29/808

CPC classification number: H01L29/808 ,  H01L21/048 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66901

Abstract: On a p− epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p− epitaxial layer a voltage that causes a reverse biased state of the p− epitaxial layer and the n-type epitaxial layer in an OFF operation.

Abstract translation: 在p-外延层上依次形成n型外延层和栅极区。 栅电极电连接到栅极区，源电极和漏极彼此间隔开，栅电极夹在其间。 控制电极被用于向p-外延层施加一个电压，该电压导致p型外延层和n型外延层在OFF操作中的反向偏压状态。

公开(公告)号：US20100065857A1

公开(公告)日：2010-03-18

申请号：US12513554

申请日：2007-11-07

Applicant: Shin Harada ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Takeyoshi Masuda

IPC: H01L29/161 ,  H01L21/04

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02639 ,  H01L21/0445 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. A coating film made of Si is formed on an initial growth layer on a 4H—SiC substrate, and an extended terrace surface is formed in a region covered with the coating film. Next, the coating film is removed, and a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion made of 3C—SiC crystals having a polytype stable at a low temperature is grown on the extended terrace surface of the initial growth layer. A channel region of a MOSFET or the like is provided in the 3C—SiC portion having a narrow band gap. As a result, the channel mobility is improved because of a reduction in an interface state, and a silicon carbide semiconductor device having excellent performance characteristics is obtained.

Abstract translation: 获得具有优异性能的碳化硅半导体器件及其制造方法。 在4H-SiC基板上的初始生长层上形成由Si制成的涂膜，在被覆膜覆盖的区域中形成延伸的台阶表面。 接着，除去涂膜，在初始生长层上外延生长新的生长层。 在初始生长层的延伸平台表面上生长由低温下具有多型稳定性的3C-SiC晶体制成的3C-SiC部分。 在具有窄带隙的3C-SiC部分中提供MOSFET等的沟道区域。 结果，由于接口状态的降低，沟道迁移率得到改善，并且获得了具有优异性能的碳化硅半导体器件。

公开(公告)号：US06807327B2

公开(公告)日：2004-10-19

申请号：US10411270

申请日：2003-04-11

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: G02B622

CPC classification number: G02B6/132 ,  G02F1/025 ,  G02F2201/066

Abstract: A multilayer semiconductor portion is provided on a semiconductor substrate on side faces of a semiconductor portion. A second conductive type III-V compound semiconductor layer is provided on the semiconductor portion and the multilayer semiconductor portion. The multilayer semiconductor portion has first to fourth semiconductor layers sequentially arranged on the semiconductor substrate. The first semiconductor layer is a first conductive type III-V compound semiconductor layer extending along the side face of the semiconductor portion and a principal surface of the semiconductor substrate. The second semiconductor layer is a second conductive type III-V group compound semiconductor layer extending along the first semiconductor layer. The third semiconductor layer is a first conductive type III-V compound semiconductor layer extending along the second semiconductor layer. The fourth semiconductor layer is a second conductive type III-V compound semiconductor layer provided on the third semiconductor layer.

Abstract translation: 在半导体基板的半导体部分的侧面上设置有多层半导体部。 在半导体部分和多层半导体部分上设置第二导电型III-V化合物半导体层。 多层半导体部分具有顺序地布置在半导体衬底上的第一至第四半导体层。 第一半导体层是沿着半导体部分的侧面和半导体衬底的主表面延伸的第一导电型III-V化合物半导体层。 第二半导体层是沿着第一半导体层延伸的第二导电型III-V族化合物半导体层。 第三半导体层是沿第二半导体层延伸的第一导电型III-V族化合物半导体层。 第四半导体层是设置在第三半导体层上的第二导电型III-V族化合物半导体层。

公开(公告)号：US09012922B2

公开(公告)日：2015-04-21

申请号：US13607388

申请日：2012-09-07

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC: H01L29/15 ,  H01L31/0312 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/3065 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/0475 ,  H01L21/3081 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7813 ,  Y10S438/931

Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.

Abstract translation: 衬底设置有相对于参考平面具有5°或更小偏离角的主表面。 在六边形系统的情况下，参考平面为{000-1}平面，在立方体系的情况下为{111}面。 在基板的主表面上外延形成碳化硅层。 碳化硅层设置有具有彼此相对的第一和第二侧壁的沟槽。 第一和第二侧壁中的每一个包括通道区域。 此外，在六边形系统的情况下，第一和第二侧壁中的每一个基本上包括{0-33-8}面和{01-1-4}面之一，并且在 立方体系的情况。