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公开(公告)号：US08921903B2
公开(公告)日：2014-12-30
申请号：US12517761
申请日：2007-09-21
申请人： Takeyoshi Masuda , Yasuo Namikawa
发明人： Takeyoshi Masuda , Yasuo Namikawa
CPC分类号： H01L29/808 , H01L21/048 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/66901
摘要： On a p− epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p− epitaxial layer a voltage that causes a reverse biased state of the p− epitaxial layer and the n-type epitaxial layer in an OFF operation.
摘要翻译： 在p-外延层上依次形成n型外延层和栅极区。 栅电极电连接到栅极区，源电极和漏极彼此间隔开，栅电极夹在其间。 控制电极被用于向p-外延层施加一个电压，该电压导致p型外延层和n型外延层在OFF操作中的反向偏压状态。
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公开(公告)号：US20100044721A1
公开(公告)日：2010-02-25
申请号：US12526731
申请日：2008-08-21
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/67109 , H01L29/45 , H01L29/66068 , Y10T117/1068 , Y10T117/1088
摘要： The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件能够通过在热处理步骤中充分抑制晶片的表面粗糙化以及其中性能恶化的半导体器件来抑制由于晶片的表面粗糙而导致的性能恶化 造成表面粗糙度受到抑制。 制造作为半导体器件的MOSFET的方法具有制备由碳化硅制成的晶片3的步骤和通过加热晶片3进行活化退火的活化退火步骤。在活化退火步骤中，晶片3被加热 在包含由除了晶片3之外的发生源的SiC片61产生的碳化硅蒸气的气氛中。
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3.发明申请METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE 审中-公开制造碳化硅衬底的方法，制造半导体器件的方法，碳化硅衬底和半导体器件公开(公告)号：US20120126251A1
公开(公告)日：2012-05-24
申请号：US13388691
申请日：2011-02-25
申请人： Makoto Sasaki , Shin Harada , Takeyoshi Masuda , Keiji Wada , Hiroki Inoue , Taro Nishiguchi , Kyoko Okita , Yasuo Namikawa , Taku Horii
发明人： Makoto Sasaki , Shin Harada , Takeyoshi Masuda , Keiji Wada , Hiroki Inoue , Taro Nishiguchi , Kyoko Okita , Yasuo Namikawa , Taku Horii
CPC分类号： H01L29/7802 , H01L21/2007 , H01L21/3247 , H01L29/045 , H01L29/1608 , H01L29/66068
摘要： A method for manufacturing a silicon carbide substrate achieves reduced manufacturing cost. The method includes the steps of: preparing a base substrate and a SiC substrate; fabricating a stacked substrate by stacking the base substrate and the SiC substrate; fabricating a connected substrate by heating the stacked substrate; transferring a void, formed at a connection interface, in a thickness direction of the connected substrate by heating the connected substrate to cause the base substrate to have a temperature higher than that of the SiC substrate; and removing the void by removing a region including a main surface of the base substrate opposite to the SiC substrate.
摘要翻译： 制造碳化硅衬底的方法降低了制造成本。 该方法包括以下步骤：制备基底和SiC衬底; 通过堆叠基底基板和SiC基板来制造堆叠的基板; 通过加热堆叠的基板来制造连接的基板; 通过加热连接的基板，在连接的基板的厚度方向上形成在连接界面处形成的空隙，使得基底基板的温度高于SiC基板的温度; 并且通过去除包括与SiC衬底相对的基底衬底的主表面的区域来去除空隙。
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公开(公告)号：US20120056201A1
公开(公告)日：2012-03-08
申请号：US13320243
申请日：2010-04-27
申请人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga , Taro Nishiguchi , Makoto Sasaki , Shinsuke Fujiwara , Yasuo Namikawa
发明人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga , Taro Nishiguchi , Makoto Sasaki , Shinsuke Fujiwara , Yasuo Namikawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7802 , C30B23/00 , C30B29/36 , C30B33/06 , H01L21/02378 , H01L21/02529 , H01L21/2007 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/7395
摘要： An IGBT, which is a vertical type IGBT allowing for reduced on-resistance while restraining defects from being produced, includes: a silicon carbide substrate, a drift layer, a well region, an n+ region, an emitter contact electrode, a gate oxide film, a gate electrode, and a collector electrode. The silicon carbide substrate includes: a base layer made of silicon carbide and having p type conductivity; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The base layer has a p type impurity concentration exceeding 1×1018 cm−3.
摘要翻译： IGBT是一种允许在抑制缺陷产生的同时降低导通电阻的垂直型IGBT，包括：碳化硅衬底，漂移层，阱区，n +区，发射极接触电极，栅极氧化膜 ，栅电极和集电极。 碳化硅基板包括：由碳化硅制成并具有p型导电性的基底层; 以及由单晶碳化硅制成并设置在基底层上的SiC层。 基极层的p型杂质浓度超过1×1018cm-3。
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公开(公告)号：US20120056202A1
公开(公告)日：2012-03-08
申请号：US13320247
申请日：2010-04-27
申请人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga , Makoto Sasaki , Taro Nishiguchi , Yasuo Namikawa , Shinsuke Fujiwara
发明人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga , Makoto Sasaki , Taro Nishiguchi , Yasuo Namikawa , Shinsuke Fujiwara
IPC分类号： H01L29/24
CPC分类号： H01L29/7802 , C30B23/00 , C30B29/36 , C30B33/06 , H01L21/02378 , H01L21/02529 , H01L21/2007 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/7395
摘要： A MOSFET, which is a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source contact electrode disposed on the active layer; and a drain electrode formed on the other main surface of the silicon carbide substrate. The silicon carbide substrate includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. Further, the base layer has an impurity concentration greater than 2×1019 cm−3, and the SiC layer has an impurity concentration greater than 5×1018 cm−3 and smaller than 2×1019 cm−3.
摘要翻译： 一种MOSFET，其是在器件制造工艺中由于热处理而允许抑制堆垛层错而产生降低的导通电阻的半导体器件，包括：碳化硅衬底; 由单晶碳化硅构成的有源层，设置在碳化硅基板的一个主面上; 设置在有源层上的源极接触电极; 以及形成在碳化硅衬底的另一个主表面上的漏电极。 碳化硅基板包括：由碳化硅制成的基层; 以及由单晶碳化硅制成并设置在基底层上的SiC层。 此外，基底层的杂质浓度大于2×1019cm-3，并且SiC层的杂质浓度大于5×1018cm-3且小于2×1019cm-3。
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6.发明申请METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE 审中-公开制造碳化硅基板，碳化硅基板和半导体器件的方法公开(公告)号：US20120012862A1
公开(公告)日：2012-01-19
申请号：US13258801
申请日：2010-09-29
申请人： Taro Nishiguchi , Makoto Sasaki , Shin Harada , Shinsuke Fujiwara , Yasuo Namikawa , Takeyoshi Masuda
发明人： Taro Nishiguchi , Makoto Sasaki , Shin Harada , Shinsuke Fujiwara , Yasuo Namikawa , Takeyoshi Masuda
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/0475 , H01L21/187 , H01L29/045 , H01L29/1608 , H01L29/66068
摘要： A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; and connecting the base substrate and SiC substrate to each other by forming an intermediate layer, which is made of carbon that is a conductor, between the base substrate and the SiC substrate.
摘要翻译： 制造碳化硅基板的方法包括以下步骤：制备由碳化硅制成的基底基板和由单晶碳化硅制成的SiC基板; 并且通过在基底基板和SiC基板之间形成由导电体的碳制成的中间层，将基底基板与SiC基板相互连接。
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公开(公告)号：US08697555B2
公开(公告)日：2014-04-15
申请号：US12526731
申请日：2008-08-21
IPC分类号： H01L21/265
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/67109 , H01L29/45 , H01L29/66068 , Y10T117/1068 , Y10T117/1088
摘要： The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件能够通过在热处理步骤中充分抑制晶片的表面粗糙化以及其中性能恶化的半导体器件来抑制由于晶片的表面粗糙而导致的性能恶化 造成表面粗糙度受到抑制。 制造作为半导体器件的MOSFET的方法具有制备由碳化硅制成的晶片3的步骤和通过加热晶片3进行活化退火的活化退火步骤。在活化退火步骤中，晶片3被加热 在包含由除了晶片3之外的发生源的SiC片61产生的碳化硅蒸气的气氛中。
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8.发明申请METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE 审中-公开制造碳化硅基体和碳化硅基体的方法公开(公告)号：US20120025208A1
公开(公告)日：2012-02-02
申请号：US13258907
申请日：2010-09-29
申请人： Taro Nishiguchi , Takeyoshi Masuda , Makoto Sasaki , Shin Harada , Yasuo Namikawa , Shinsuke Fujiwara
发明人： Taro Nishiguchi , Takeyoshi Masuda , Makoto Sasaki , Shin Harada , Yasuo Namikawa , Shinsuke Fujiwara
IPC分类号： H01L29/161 , H01L21/762
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/0475 , H01L21/187 , H01L29/045 , H01L29/1608 , H01L29/66068
摘要： A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; forming a Si film made of silicon on a main surface of the base substrate; fabricating a stacked substrate by placing the SiC substrate on and in contact with the Si film; and connecting the base substrate and the SiC substrate to each other by heating the stacked substrate to convert, into silicon carbide, at least a region making contact with the base substrate and a region making contact with the SiC substrate in the Si film.
摘要翻译： 制造碳化硅基板的方法包括以下步骤：制备由碳化硅制成的基底基板和由单晶碳化硅制成的SiC基板; 在所述基底基板的主表面上形成由硅制成的Si膜; 通过将SiC衬底置于Si膜上并与其接触来制造堆叠衬底; 并且通过加热所述堆叠的基板将所述基底基板和所述SiC基板彼此连接，以将至少与所述基底基板接触的区域和与所述Si膜中的所述SiC基板接触的区域转化为碳化硅。
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公开(公告)号：US20100090259A1
公开(公告)日：2010-04-15
申请号：US12517761
申请日：2007-09-21
申请人： Takeyoshi Masuda , Yasuo Namikawa
发明人： Takeyoshi Masuda , Yasuo Namikawa
IPC分类号： H01L29/808
CPC分类号： H01L29/808 , H01L21/048 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/66901
摘要： On a p− epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p− epitaxial layer a voltage that causes a reverse biased state of the p− epitaxial layer and the n-type epitaxial layer in an OFF operation.
摘要翻译： 在p-外延层上依次形成n型外延层和栅极区。 栅电极电连接到栅极区，源电极和漏极彼此间隔开，栅电极夹在其间。 控制电极被用于向p-外延层施加一个电压，该电压导致p型外延层和n型外延层在OFF操作中的反向偏压状态。
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10.发明申请公开(公告)号：US20120061686A1
公开(公告)日：2012-03-15
申请号：US13319560
申请日：2010-04-27
IPC分类号： H01L29/02 , H01L21/762
CPC分类号： H01L29/7802 , C30B23/00 , C30B29/36 , C30B33/06 , H01L21/02378 , H01L21/02529 , H01L21/2007 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/7395
摘要： A silicon carbide substrate allowing reduction in cost for manufacturing a semiconductor device including a silicon carbide substrate includes a base substrate composed of silicon carbide and an SiC layer composed of single crystal silicon carbide different from the base substrate and arranged on the base substrate in contact therewith. Thus, the silicon carbide substrate 1 is a silicon carbide substrate capable of making effective use of silicon carbide single crystal.
摘要翻译： 允许降低制造包括碳化硅衬底的半导体器件的成本的碳化硅衬底包括由碳化硅构成的基底衬底和由与基底基板不同的单晶碳化硅构成的SiC层，并与基底衬底接触地布置 。 因此，碳化硅衬底1是能够有效利用碳化硅单晶的碳化硅衬底。
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