公开(公告)号：US20190295971A1

公开(公告)日：2019-09-26

申请号：US16436626

申请日：2019-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/768

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

公开(公告)号：US20170229421A1

公开(公告)日：2017-08-10

申请号：US15497408

申请日：2017-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen Tseng ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/00

CPC classification number: H01L24/15 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/283 ,  H01L21/44 ,  H01L21/47 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02333 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. A method of forming a device includes forming a conductive trace over a first substrate, the conductive trace having first tapering sidewalls, forming a conductive bump over a second substrate, the conductive bump having second tapering sidewalls and a first surface distal the second substrate, and attaching the conductive bump to the conductive trace via a solder region. The solder region extends from the first surface of the conductive bump to the first substrate, and covers the first tapering sidewalls of the conductive trace. The second tapering sidewalls of the conductive bump are free of the solder region.

公开(公告)号：US20150357301A1

公开(公告)日：2015-12-10

申请号：US14828147

申请日：2015-08-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guan-Yu Chen ,  Yu-Wei Lin ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Abstract translation: 轨迹（BOT）结构上的实施例凸块包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下金属（UBM）特征，凸起下金属冶金特征上的金属凸块，以及衬底迹线 衬底，通过焊接接头和金属间化合物耦合到金属凸块的衬底迹线，金属间化合物的第一横截面积与焊料接头的第二横截面积的比率大于百分之四十。

公开(公告)号：US20140167253A1

公开(公告)日：2014-06-19

申请号：US13719019

申请日：2012-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen Tseng ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L24/15 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/283 ,  H01L21/44 ,  H01L21/47 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02333 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.

Abstract translation: 公开了半导体器件，其制造方法和封装的半导体器件。 在一个实施例中，半导体器件包括衬底和设置在衬底上的导电迹线。 每个导电迹线具有靠近衬底的底部区域和与底部区域相对的顶部区域。 顶部区域具有第一宽度，底部区域具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US09966346B2

公开(公告)日：2018-05-08

申请号：US14828147

申请日：2015-08-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guan-Yu Chen ,  Yu-Wei Lin ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

公开(公告)号：US09953939B2

公开(公告)日：2018-04-24

申请号：US15356316

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

公开(公告)号：US09646923B2

公开(公告)日：2017-05-09

申请号：US13719019

申请日：2012-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen Tseng ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L23/488 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/15 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/283 ,  H01L21/44 ,  H01L21/47 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02333 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.

公开(公告)号：US20150325542A1

公开(公告)日：2015-11-12

申请号：US14804617

申请日：2015-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

Abstract translation: 凸块结构包括形成在衬底上的接触元件和覆盖衬底的钝化层。 钝化层包括暴露接触元件的钝化开口。 凸块结构还包括覆盖钝化层的聚酰亚胺层和电耦合到接触元件的凸块下冶金（UBM）特征。 聚酰亚胺层具有暴露接触元件的聚酰亚胺开口，凸起下的金属特征具有UBM宽度。 凸起结构还包括在凸起下金属冶金特征上的铜柱。 铜柱的前端具有柱宽，UBM宽度大于柱宽。

公开(公告)号：US09105530B2

公开(公告)日：2015-08-11

申请号：US13904885

申请日：2013-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar width, and the UBM width is greater than the pillar width.

Abstract translation: 凸块结构包括形成在衬底上的接触元件和覆盖衬底的钝化层。 钝化层包括暴露接触元件的钝化开口。 凸起结构还包括覆盖钝化层的聚酰亚胺层和电耦合到接触元件的凸块下金属（UBM）特征。 聚酰亚胺层具有暴露接触元件的聚酰亚胺开口，凸起下的金属特征具有UBM宽度。 凸起结构还包括在凸起下金属冶金特征上的铜柱。 铜柱宽度的远端，UBM宽度大于柱宽。

公开(公告)号：US10319691B2

公开(公告)日：2019-06-11

申请号：US15351184

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.