公开(公告)号：US20230395443A1

公开(公告)日：2023-12-07

申请号：US17805566

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Li-Ling LIAO ,  Yu-Sheng LIN ,  Shin-Puu JENG

IPC分类号： H01L23/13 ,  H01L23/00 ,  H01L25/16 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L21/4846 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/1436 ,  H01L2924/1431 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/15153

摘要： A semiconductor package, which may correspond to a high-performance computing package, includes an interposer, a substrate, and an integrated circuit device between the interposer and the substrate. The integrated circuit device, which may correspond to an integrated passive device, is attached to the interposer within a cavity of the interposer. Attaching the integrated circuit device within the cavity of the interposer creates a clearance between the integrated circuit device and the substrate. In this way, a likelihood of the integrated circuit device contacting the substrate during a bending and/or a deformation of the semiconductor package is reduced. By reducing the likelihood of such contact, damage to the integrated circuit device and/or the substrate may be avoided to increase a reliability and/or yield of the semiconductor package.

公开(公告)号：US20230378055A1

公开(公告)日：2023-11-23

申请号：US18358491

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Wen WU ,  Techi WONG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Shih-Ting HUNG ,  Shin-Puu JENG

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

CPC分类号： H01L23/5226 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L23/481 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5283 ,  H01L21/563 ,  H01L21/561 ,  H01L24/09 ,  H01L2224/73203 ,  H01L2224/0401 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/02373

摘要： A semiconductor package is provided. The semiconductor package includes a redistribution structure, a semiconductor die, and an interposer structure. The interposer structure includes an insulating base having a first surface facing the semiconductor die and a second surface opposite to the first surface and conductive features formed over the insulating base. The conductive features include first portions on the first surface of the insulating base and vertically overlapping the semiconductor die, second portions on the first surface of the insulating base and located outside a projection area of the semiconductor die in a top view, third portions on the second surface of the insulating base and vertically overlapping the semiconductor die, and fourth portions on the second surface of the insulating base and located outside the projection area of the semiconductor die in the top view. The interposer structure includes capping layers and dielectric features.

公开(公告)号：US20230361016A1

公开(公告)日：2023-11-09

申请号：US17662366

申请日：2022-05-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei CHEN ,  Meng-Liang LIN ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49894 ,  H01L25/0655 ,  H01L24/16 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

摘要： A semiconductor package, which may correspond to a high-performance computing package, includes an interposer over a substrate. A spacer structure is mounted to a bottom surface of the interposer. The spacer structure is configured to maintain a clearance between a bottom surface of an integrated circuit die mounted to the bottom surface of the interposer and a top surface of the substrate to reduce a likelihood of an interference or collision between the integrated circuit die and the substrate. In this way, a likelihood of damage to the integrated circuit die and/or the substrate is reduced. Additionally, a robustness of an electrical connection between the integrated circuit die and the interposer may increase to improve a reliability and/or a yield of the semiconductor package including the spacer structure.

公开(公告)号：US20230343725A1

公开(公告)日：2023-10-26

申请号：US18344039

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Chia-Kuei HSU ,  Li-Ling LIAO ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/5383 ,  H01L21/4853 ,  H01L23/5386 ,  H01L25/50 ,  H01L25/0655 ,  H01L2224/73204 ,  H01L24/16 ,  H01L2224/16238 ,  H01L24/73

摘要： A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.

公开(公告)号：US20230016849A1

公开(公告)日：2023-01-19

申请号：US17377620

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Huei LEE ,  Shu-Shen YEH ,  Kuo-Ching HSU ,  Shyue-Ter LEU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/498

摘要： A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

公开(公告)号：US20220384391A1

公开(公告)日：2022-12-01

申请号：US17818432

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG ,  Po-Chen LAI ,  Kuang-Chun LEE ,  Che-Chia YANG ,  Chin-Hua WANG ,  Yi Hang LIN

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure and a second chip structure over the wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The chip package structure includes a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

公开(公告)号：US20220384390A1

公开(公告)日：2022-12-01

申请号：US17817705

申请日：2022-08-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Chia YANG ,  Shu-Shen YEH ,  Po-Chen LAI ,  Ming-Chih YEW ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

摘要： A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

公开(公告)号：US20220367314A1

公开(公告)日：2022-11-17

申请号：US17318163

申请日：2021-05-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Che-Chia YANG ,  Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/373 ,  H01L23/29 ,  H01L23/58

摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.

公开(公告)号：US20220361338A1

公开(公告)日：2022-11-10

申请号：US17396253

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Chen LAI ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H05K1/18 ,  H05K3/28 ,  H01L25/065

摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate, a semiconductor device, an underfill element, and a groove. The semiconductor device is bonded to the surface of the package substrate through multiple electrical connectors. The underfill element is formed between the semiconductor device and the surface of the package substrate to surround and protect the electrical connectors. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The groove is formed in the fillet portion and spaced apart from the periphery of the semiconductor device.

公开(公告)号：US20220189884A1

公开(公告)日：2022-06-16

申请号：US17688647

申请日：2022-03-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Yao CHUANG ,  Po-Hao TSAI ,  Shin-Puu JENG ,  Shuo-Mao CHEN ,  Ming-Chih YEW

IPC分类号： H01L23/552 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H05K1/02 ,  H01L23/498 ,  H01L25/16

摘要： A method for forming a chip package is provided. The method includes forming a plurality of conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive ti structures surround the semiconductor die. The method further includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.