-
公开(公告)号：US20200075320A1
公开(公告)日：2020-03-05
申请号：US16430114
申请日：2019-06-03
发明人： Dong-Sheng Li , Chia-Hui Lin , Kai Hung Cheng , Yao-Hsu Sun , Wen-Cheng Wu , Bo-Cyuan Lu , Sung-En Lin , Tai-Chun Huang
IPC分类号： H01L21/027 , H01L21/033 , H01L21/02 , H01L21/28 , H01L21/3213 , H01L21/311 , H01L21/8238
摘要： A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
-
公开(公告)号：US10535569B2
公开(公告)日：2020-01-14
申请号：US16048483
申请日：2018-07-30
发明人： Kai-Hsuan Lee , Chia-Ta Yu , Cheng-Yu Yang , Sheng-Chen Wang , Bo-Yu Lai , Bo-Cyuan Lu , Chi On Chui , Sai-Hooi Yeong , Feng-Cheng Yang , Yen-Ming Chen
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/08 , H01L21/8234 , H01L29/66
摘要： A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
-
公开(公告)号：US20180315840A1
公开(公告)日：2018-11-01
申请号：US15694636
申请日：2017-09-01
发明人： Chi On Chui , Bo-Cyuan Lu
CPC分类号： H01L29/66818 , H01L21/02126 , H01L21/0217 , H01L21/0228 , H01L21/02304 , H01L21/02312 , H01L21/28132 , H01L21/3105 , H01L21/32 , H01L29/66545 , H01L29/66553
摘要： A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each deposition cycle includes adsorbing a first precursor over the second surface, performing a first purge process, adsorbing a second precursor over the second surface, and performing a second purge process. The method also includes performing a third purge process that is different from the first purge process or the second purge process.
-
14.发明授权公开(公告)号：US11264383B2
公开(公告)日：2022-03-01
申请号：US17024006
申请日：2020-09-17
发明人： Chun-Han Chen , Chen-Ming Lee , Fu-Kai Yang , Mei-Yun Wang , Jr-Hung Li , Bo-Cyuan Lu
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/423 , H01L29/66 , H01L29/78
摘要： A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.
-
公开(公告)号：US10861959B2
公开(公告)日：2020-12-08
申请号：US16511764
申请日：2019-07-15
发明人： Chi On Chui , Bo-Cyuan Lu
IPC分类号： H01L21/02 , H01L21/28 , H01L21/3105 , H01L21/32 , H01L29/66
摘要： A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each deposition cycle includes adsorbing a first precursor over the second surface, performing a first purge process, adsorbing a second precursor over the second surface, and performing a second purge process. The method also includes performing a third purge process that is different from the first purge process or the second purge process.
-
公开(公告)号：US10734227B2
公开(公告)日：2020-08-04
申请号：US16430114
申请日：2019-06-03
发明人： Dong-Sheng Li , Chia-Hui Lin , Kai Hung Cheng , Yao-Hsu Sun , Wen-Cheng Wu , Bo-Cyuan Lu , Sung-En Lin , Tai-Chun Huang
IPC分类号： H01L21/027 , H01L21/033 , H01L21/02 , H01L21/28 , H01L21/3213 , H01L21/311 , H01L21/8238 , G03F7/09 , G03F7/16 , G03F7/20 , G03F7/26
摘要： A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
-
公开(公告)号：US20200152522A1
公开(公告)日：2020-05-14
申请号：US16740895
申请日：2020-01-13
发明人： Kai-Hsuan Lee , Chia-Ta Yu , Cheng-Yu Yang , Sheng-Chen Wang , Bo-Yu Lai , Bo-Cyuan Lu , Chi On Chui , Sai-Hooi Yeong , Feng-Cheng Yang , Yen-Ming Chen
IPC分类号： H01L21/8238 , H01L29/08 , H01L29/49 , H01L27/092 , H01L29/66 , H01L21/8234
摘要： A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.019 秒)
