公开(公告)号：US10526196B2

公开(公告)日：2020-01-07

申请号：US15873937

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Chun-Yin Tsai ,  Chia-Hua Chu ,  Chun-Wen Cheng

IPC: H01L41/113 ,  B81B3/00 ,  B81C1/00 ,  H04R19/00

Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a first dielectric layer and a second dielectric layer over a semiconductor substrate. A cavity penetrates through the first dielectric layer and the second dielectric layer. The semiconductor device structure also includes a first movable membrane between the first dielectric layer and the second dielectric layer. The first movable membrane is partially exposed through the cavity. The first movable membrane includes first corrugated portions arranged along an edge of the cavity.

公开(公告)号：US09269679B2

公开(公告)日：2016-02-23

申请号：US14072141

申请日：2013-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Li-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC: H01L21/66 ,  H01L23/00 ,  B81C99/00

CPC classification number: H01L24/06 ,  B81B2207/012 ,  B81C99/0045 ,  B81C99/005 ,  H01L22/32 ,  H01L23/10 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/0605 ,  H01L2224/32145 ,  H01L2224/83194 ,  H01L2924/01322 ,  H01L2924/16235 ,  H01L2924/00

Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

Abstract translation: 在用于MEMS器件的晶片级芯片级封装技术中，首先在CMOS衬底的两个CMOS器件之间的刻划线区域上蚀刻深沟槽。 在将CMOS衬底与MEMS衬底结合之后，通过薄层化工艺来打开深沟槽，使得在衬底不是（部分单片化）的情况下将CMOS衬底分离。 MEMS基板上的电测试板被暴露，保护材料可以通过粘结层周围的深沟槽填充。 在填充保护材料之后，将晶片切割成形成封装的独立芯片，保护结合层外部的环境。

公开(公告)号：US08841201B2

公开(公告)日：2014-09-23

申请号：US13771382

申请日：2013-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Hsin-Ting Huang ,  Lin-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC: H01L21/46 ,  H01L29/06 ,  H01L21/18

CPC classification number: H01L21/185 ,  B81C1/00269 ,  B81C2201/053 ,  B81C2203/0118 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/564 ,  H01L29/06 ,  H01L2224/94 ,  H01L2924/18161 ,  H01L2224/83

Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.

Abstract translation: 公开了一种制造半导体器件的方法。 第一衬底被布置在第二衬底上。 在半导体器件上进行晶片接合处理。 设备的第一个区域由绑定过程包围。 设备的第二个区域保持暴露。 在进行晶片接合处理之后，在暴露的第二区域上执行一个或多个处理。 一个或多个过程包括在暴露的第二区域内形成填充材料的填充过程。 在执行一个或多个处理之后，在第一和第二基板上施加边缘密封材料。

公开(公告)号：US11292712B2

公开(公告)日：2022-04-05

申请号：US16731183

申请日：2019-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Chun-Yin Tsai ,  Chia-Hua Chu ,  Chun-Wen Cheng

IPC: H01L41/113 ,  B81B3/00 ,  B81C1/00 ,  H04R19/00

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first dielectric layer over a substrate and forming a first recess in the first dielectric layer. The method also includes conformally forming a first movable membrane over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion in the first recess. The method further includes forming a second dielectric layer over the first movable membrane and partially removing the substrate, the first dielectric layer, and the second dielectric layer to form a cavity. In addition, the first corrugated portion of the first movable membrane is partially sandwiched between the first dielectric layer and the second dielectric layer.

公开(公告)号：US11276670B2

公开(公告)日：2022-03-15

申请号：US16851114

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Victor Chiang Liang ,  Jung-Kuo Tu ,  Ching-Kai Shen

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.

公开(公告)号：US10861929B2

公开(公告)日：2020-12-08

申请号：US16163782

申请日：2018-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Fung Chang ,  Lien-Yao Tsai ,  Baohua Niu ,  Yi-Chuan Teng ,  Chi-Yuan Shih

IPC: H01L49/02 ,  H01G4/06 ,  H01L41/047 ,  B81B3/00 ,  B81B7/02 ,  B81C1/00

Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.

公开(公告)号：US20200339412A1

公开(公告)日：2020-10-29

申请号：US16923869

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Hung-Chia Tsai ,  Yi-Chuan Teng

IPC: B81B7/00 ,  B81C1/00 ,  B81B7/02

Abstract: An embodiment is a MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.

公开(公告)号：US20200098517A1

公开(公告)日：2020-03-26

申请号：US16417797

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anderson Lin ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yen-Wen Chen ,  Fu-Chun Huang ,  Fan Hu ,  Ching-Hui Lin ,  Yan-Jie Liao

IPC: H01G4/012 ,  H01G4/228 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01G4/12

Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.

公开(公告)号：US20150123129A1

公开(公告)日：2015-05-07

申请号：US14072141

申请日：2013-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Li-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L24/06 ,  B81B2207/012 ,  B81C99/0045 ,  B81C99/005 ,  H01L22/32 ,  H01L23/10 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/0605 ,  H01L2224/32145 ,  H01L2224/83194 ,  H01L2924/01322 ,  H01L2924/16235 ,  H01L2924/00

Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

Abstract translation: 在用于MEMS器件的晶片级芯片级封装技术中，首先在CMOS衬底的两个CMOS器件之间的刻划线区域上蚀刻深沟槽。 在将CMOS衬底与MEMS衬底结合之后，通过薄层化工艺来打开深沟槽，使得在衬底不是（部分单片化）的情况下将CMOS衬底分离。 MEMS基板上的电测试板被暴露，保护材料可以通过粘结层周围的深沟槽填充。 在填充保护材料之后，将晶片切割成形成封装的独立芯片，保护结合层外部的环境。