公开(公告)号：US20160149040A1

公开(公告)日：2016-05-26

申请号：US14819602

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chia-Ling CHAN ,  Chien-Tai CHAN

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.

Abstract translation: FinFET包括鳍结构，栅极和源极 - 漏极区域。 翅片结构在衬底之上，并且具有翅片结构的上表面的凹部和鳍结构中的与凹部相邻的掺杂区域。 门从凹槽突出并跨过翅片结构。 源极 - 漏极区域处于鳍状结构并且与掺杂区域相邻。 还提供了形成FinFET的方法。

公开(公告)号：US20150228791A1

公开(公告)日：2015-08-13

申请号：US14697656

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Yuan-Ching PENG ,  Chun-Hsiung TSAI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.

Abstract translation: 描述了具有改进性能的半导体子结构及其形成方法。 在一个实施例中，半导体子结构包括具有上表面的基板; 形成在所述基板上的栅极结构; 沿所述栅极结构的侧壁形成的间隔物; 以及邻近栅极结构设置的源极/漏极结构。 源极/漏极结构由应变材料形成，并且设置在在衬底的上表面下方延伸的凹部中。 间隔物和源极 - 漏极结构之间的界面可以在衬底的上表面上方至少2nm。

公开(公告)号：US20140197455A1

公开(公告)日：2014-07-17

申请号：US13739010

申请日：2013-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Yuan-Ching PENG ,  Chun-Hsiung TSAI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.

Abstract translation: 描述了具有改进性能的半导体子结构及其形成方法。 在一个实施例中，半导体子结构包括具有上表面的基板; 形成在所述基板上的栅极结构; 沿所述栅极结构的侧壁形成的间隔物; 以及邻近栅极结构设置的源极/漏极结构。 源极/漏极结构由应变材料形成，并且设置在在衬底的上表面下方延伸的凹部中。 间隔物和源极 - 漏极结构之间的界面可以在衬底的上表面上方至少2nm。

公开(公告)号：US20240088155A1

公开(公告)日：2024-03-14

申请号：US18510370

申请日：2023-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31111

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

公开(公告)号：US20220384442A1

公开(公告)日：2022-12-01

申请号：US17885383

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.

公开(公告)号：US20220336612A1

公开(公告)日：2022-10-20

申请号：US17548179

申请日：2021-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung CHANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Chia-Pin LIN ,  Wei-Yang LEE ,  Yen-Sheng LU

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

公开(公告)号：US20200135590A1

公开(公告)日：2020-04-30

申请号：US16412007

申请日：2019-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.

公开(公告)号：US20230253478A1

公开(公告)日：2023-08-10

申请号：US18297824

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsieh WONG ,  Wei-Yang LEE ,  Yen-Ming CHEN ,  Feng-Cheng YANG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/0649 ,  H01L21/02293 ,  H01L29/511 ,  H01L29/66636 ,  H01L21/022 ,  H01L29/66553

Abstract: A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

公开(公告)号：US20220093743A1

公开(公告)日：2022-03-24

申请号：US17027302

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US20210273101A1

公开(公告)日：2021-09-02

申请号：US17320687

申请日：2021-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chii-Horng LI ,  Feng-Cheng YANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.