公开(公告)号：US20180122739A1

公开(公告)日：2018-05-03

申请号：US15855795

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hua CHEN ,  Tai-I YANG ,  Cheng-Chi CHUANG ,  Chia-Tien WU ,  Tien-Lu LIN ,  Tien-I BAO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.

公开(公告)号：US20220157649A1

公开(公告)日：2022-05-19

申请号：US17649503

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US20210057522A1

公开(公告)日：2021-02-25

申请号：US17091595

申请日：2020-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tien-Lu LIN ,  Jung-Hung CHANG

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: A method includes forming a pad layer and a mask layer over a substrate; patterning the mask layer, the pad layer, and the substrate to form pads, masks, and first and semiconductor fins over the substrate; forming a liner covering the pads, the masks, and the first and second semiconductor fins; removing a first portion of the liner to expose sidewalls of the first semiconductor fin, while leaving a second portion of the liner covering sidewalls of the second semiconductor fin; forming an isolation material over the substrate; and performing a CMP process to the isolation material until a first one of the pads over the second semiconductor fin is exposed; and etching back the isolation material and the second portion of the liner.

公开(公告)号：US20190019753A1

公开(公告)日：2019-01-17

申请号：US16124567

申请日：2018-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Tien-I BAO ,  Tien-Lu LIN ,  Wei-Chen CHU

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphehe layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

公开(公告)号：US20170229396A1

公开(公告)日：2017-08-10

申请号：US15016866

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Tien-I BAO ,  Tien-Lu LIN ,  Wei-Chen CHU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53276

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.

公开(公告)号：US20160118336A1

公开(公告)日：2016-04-28

申请号：US14524228

申请日：2014-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tai-I YANG ,  Yu-Chieh LIAO ,  Tien-Lu LIN ,  Tien-I BAO

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L29/41758 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括半导体衬底上的第一电介质层。 半导体器件结构包括嵌入在第一介电层中的第一导线。 半导体器件结构包括在第一介电层和第一导电线上的第二介电层。 半导体器件结构包括在第二介电层上的第二导电线。 第二介电层位于第一导线与第二导线之间。 半导体器件结构包括通过第二介电层的导电柱，以将第一导电线电连接到第二导电线。 导电柱彼此间隔开。

公开(公告)号：US20230343633A1

公开(公告)日：2023-10-26

申请号：US18344965

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/31144 ,  H01L27/0886

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US20230253480A1

公开(公告)日：2023-08-10

申请号：US18301704

申请日：2023-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/7682

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

公开(公告)号：US20230141634A1

公开(公告)日：2023-05-11

申请号：US18153652

申请日：2023-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tien-Lu LIN ,  Jung-Hung CHANG

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/823878 ,  H01L21/823821 ,  H01L27/0924 ,  H01L21/823892 ,  H01L27/0921 ,  H01L21/823807 ,  H01L27/1211

Abstract: A device includes a substrate. A first semiconductor fin and a second semiconductor fin are over the substrate, wherein an upper portion of the second semiconductor fin and a lower portion of the second semiconductor fin are made of different materials. A first epitaxy structure is over the first semiconductor fin. A second epitaxy structure is in contact with the upper portion of the second semiconductor fin, wherein sidewalls of the lower portion of the second semiconductor fin are free of coverage by the second epitaxy structure. A liner is in contact with the sidewalls of the lower portion of the second semiconductor fin. An isolation structure between the first and second semiconductor fin, wherein the isolation structure is in contact with the first semiconductor fin and is separated from the second semiconductor fin through the liner.

公开(公告)号：US20210057569A1

公开(公告)日：2021-02-25

申请号：US16548423

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/308

Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.