公开(公告)号：US12218197B2

公开(公告)日：2025-02-04

申请号：US18364995

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US11908695B2

公开(公告)日：2024-02-20

申请号：US17377839

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Tsung-Ju Chen ,  Ta-Hsiang Kung ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L21/28141 ,  H01L21/0234 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

公开(公告)号：US20230138136A1

公开(公告)日：2023-05-04

申请号：US17717839

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Li ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of forming a nanostructure field-effect transistor (nano-FET) device includes: forming a fin structure that includes a fin and alternating layers of a first semiconductor material and a second semiconductor material overlying the fin; forming a dummy gate structure over the fin structure; forming source/drain regions over the fin structure on opposing sides of the dummy gate structure; removing the dummy gate structure to expose the first and second semiconductor materials under the dummy gate structure; selectively removing the exposed first semiconductor material, where after the selectively removing, the exposed second semiconductor material remains to form nanostructures, where different surfaces of the nanostructures have different atomic densities of the second semiconductor material; forming a gate dielectric layer around the nanostructures, thicknesses of the gate dielectric layer on the different surfaces of the nanostructures being formed substantially the same; and forming a gate electrode around the gate dielectric layer.

公开(公告)号：US20230117889A1

公开(公告)日：2023-04-20

申请号：US17659700

申请日：2022-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ru Lin ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure includes forming alternating first semiconductor layers and second semiconductor layers stacked over a substrate. The method also includes etching the first semiconductor layers and the second semiconductor layers to form a fin structure. The method also includes oxidizing the first semiconductor layers to form first oxidized portions of the first semiconductor layers and oxidizing the second semiconductor layers to form second oxidized portions of the second semiconductor layers. The method also includes removing the oxides over the sidewalls of the second semiconductor layers. After removing the second oxidized portions, an upper layer of the second semiconductor layers is narrower than a lower layer of the second semiconductor layers. The method also includes removing the first semiconductor layers to form a gate opening between the second semiconductor layers. The method also includes forming a gate structure in the gate opening.

公开(公告)号：US20210249271A1

公开(公告)日：2021-08-12

申请号：US16787229

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/66

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US20180166309A1

公开(公告)日：2018-06-14

申请号：US15434201

申请日：2017-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Han Chen ,  Sheng-Hung Lin ,  Han-Hsuan Hsu ,  Chien-Fang Lin

IPC: H01L21/673 ,  G05D23/19

CPC classification number: G05D23/1917 ,  G05D23/1931 ,  H01L21/67109 ,  H01L21/67248

Abstract: A system includes a cooling device, a memory, and a processor. The cooling device is configured to detect a temperature of a wafer and to provide air to the wafer. The memory is configured to store computer program codes. The processor is configured to execute the computer program codes in the memory to: determine whether the temperature of the wafer meet a predetermined requirement; adjust the temperature of the wafer on condition that the temperature does not meet the predetermined requirement; and control the cooling device to detect the temperature of the wafer again, in order to verify whether an adjusted temperature of the wafer meet predetermined requirement.

公开(公告)号：US20250089330A1

公开(公告)日：2025-03-13

申请号：US18516147

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Wei ,  Cheng-I Lin ,  Hao-Ming Tang ,  Shu-Han Chen ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming a protruding fin, and forming a first dielectric layer including a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer includes a first top portion on a top surface of the protruding fin, and a sidewall portion on a sidewall of the protruding fin. The second dielectric layer is over the first top portion and the top surface of the protruding fin, and is formed using an anisotropic deposition process. The method further includes forming a dummy gate electrode on the second dielectric layer, forming a gate spacer on a sidewall of the dummy gate electrode, removing the dummy gate electrode, and forming a replacement gate electrode in a space left by the dummy gate electrode.

公开(公告)号：US20240170563A1

公开(公告)日：2024-05-23

申请号：US18154975

申请日：2023-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Lin ,  Shu-Han Chen ,  Chi On Chui

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66545

Abstract: A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source/drain region is aside of the gate stack.

公开(公告)号：US20220102494A1

公开(公告)日：2022-03-31

申请号：US17369452

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

公开(公告)号：US20210343533A1

公开(公告)日：2021-11-04

申请号：US17377839

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Tsung-Ju Chen ,  Ta-Hsiang Kung ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/28 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/423

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.