公开(公告)号：US11227950B2

公开(公告)日：2022-01-18

申请号：US16572320

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/417 ,  H01L21/762 ,  H01L27/088

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20210091191A1

公开(公告)日：2021-03-25

申请号：US16805841

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Jung Ho ,  Jr-Hung Li ,  Tze-Liang Lee ,  Pei-Yu Chou ,  Chi-Ta Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.

公开(公告)号：US11894435B2

公开(公告)日：2024-02-06

申请号：US17193626

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/76832 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/401 ,  H01L29/7851

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

公开(公告)号：US20230327021A1

公开(公告)日：2023-10-12

申请号：US18336561

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L27/0886 ,  H01L29/41791 ,  H01L21/76224 ,  H01L21/764

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20230299136A1

公开(公告)日：2023-09-21

申请号：US17699430

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/6656 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468

Abstract: A semiconductor device including an etch stop layer and a method of forming is provided. The semiconductor device may include a source/drain region and a gate structure, wherein a first etch stop layer is over a conductive plug to a source/drain region and a second etch stop layer is over the gate structure. The first etch stop layer and the second etch stop layer may have different thicknesses. A dielectric layer may be formed over the first etch stop layer and the second etch stop layer, and contacts may be formed through the dielectric layer and the first and second etch stop layers.

公开(公告)号：US20220140142A1

公开(公告)日：2022-05-05

申请号：US17576725

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L21/764

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20210098365A1

公开(公告)日：2021-04-01

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US12293916B2

公开(公告)日：2025-05-06

申请号：US18230712

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US12046475B2

公开(公告)日：2024-07-23

申请号：US17191105

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/28247 ,  H01L21/76802 ,  H01L21/76816 ,  H01L29/401 ,  H01L29/66454 ,  H01L29/66795 ,  H01L21/31116 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/0886 ,  H01L29/41791

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US20230282750A1

公开(公告)日：2023-09-07

申请号：US17841493

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang ,  Hao-Yu Chang ,  Pei-Yu Chou

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.