公开(公告)号：US20170194201A1

公开(公告)日：2017-07-06

申请号：US14989036

申请日：2016-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang FU ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/76883 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/7688 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L29/0692

Abstract: Semiconductor structures and methods for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive structure in the trench. The method for manufacturing a semiconductor structure further includes removing the sacrificial layer. In addition, a top surface of the conductive feature is not level with a top surface of the dielectric layer after the sacrificial layer is removed.

公开(公告)号：US20200035546A1

公开(公告)日：2020-01-30

申请号：US16593562

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Jun KUO ,  Chien-Hsin HO ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US20190259658A1

公开(公告)日：2019-08-22

申请号：US16399273

申请日：2019-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

公开(公告)号：US20190131408A1

公开(公告)日：2019-05-02

申请号：US16227592

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ching-Fu YEH ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L29/16 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US20180033727A1

公开(公告)日：2018-02-01

申请号：US15220078

申请日：2016-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

公开(公告)号：US20220270915A1

公开(公告)日：2022-08-25

申请号：US17744545

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang FU ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.

公开(公告)号：US20220262675A1

公开(公告)日：2022-08-18

申请号：US17734683

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Jun Kuo ,  Chien-Hsin HO ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US20220102191A1

公开(公告)日：2022-03-31

申请号：US17033270

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang FU ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.

公开(公告)号：US20200373239A1

公开(公告)日：2020-11-26

申请号：US16988636

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A method includes depositing an etch stop layer over a non-insulator structure and a dielectric layer over the etch stop layer; etching the dielectric layer to form a first hole in the dielectric layer; deepening the first hole into the etch stop layer such that the non-insulator structure is exposed at a bottom of the deepened hole; after the non-insulator structure is exposed, performing a cleaning operation to remove etch byproducts from the deepened first hole, wherein the cleaning operation results in lateral recesses laterally extending from a bottom portion of the deepened first hole into the etch stop layer; depositing a first diffusion barrier layer into the deepened first hole until the lateral recesses are overfilled; depositing a second diffusion barrier layer over the first diffusion barrier layer; and depositing one or more conductive layers over the second diffusion barrier layer.

公开(公告)号：US20190096801A1

公开(公告)日：2019-03-28

申请号：US15715327

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.