公开(公告)号：US20210098366A1

公开(公告)日：2021-04-01

申请号：US16844133

申请日：2020-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Fang-Wei Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

公开(公告)号：US10804097B2

公开(公告)日：2020-10-13

申请号：US16568720

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/8234

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US20240387655A1

公开(公告)日：2024-11-21

申请号：US18787182

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/538 ,  H01L29/40

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US11955329B2

公开(公告)日：2024-04-09

申请号：US18309298

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Chun-I Tsai ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/02068 ,  H01L21/76871 ,  H01L21/76877

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

公开(公告)号：US11581259B2

公开(公告)日：2023-02-14

申请号：US16950537

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Chien-Shun Liao ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Shu-Lan Chang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US20220230884A1

公开(公告)日：2022-07-21

申请号：US17712480

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Kao-Feng Lin ,  Min-Hsiu Hung ,  Yi-Hsiang Chao ,  Huang-Yi Huang ,  Yu-Ting Lin

IPC: H01L21/285 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

公开(公告)号：US20220139707A1

公开(公告)日：2022-05-05

申请号：US17577726

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US10685842B2

公开(公告)日：2020-06-16

申请号：US15983216

申请日：2018-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Kao-Feng Lin ,  Min-Hsiu Hung ,  Yi-Hsiang Chao ,  Huang-Yi Huang ,  Yu-Ting Lin

IPC: H01L21/285 ,  H01L29/78 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

公开(公告)号：US12046634B2

公开(公告)日：2024-07-23

申请号：US18158148

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Shuen-Shin Liang ,  Sung-Li Wang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Chien-Shun Liao ,  Yi-Ying Liu

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US11894437B2

公开(公告)日：2024-02-06

申请号：US17320553

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chih-Chien Chi ,  Chien-Shun Liao ,  Keng-Chu Lin ,  Kai-Ting Huang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang ,  Cheng-Wei Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/45 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.