公开(公告)号：US20240088155A1

公开(公告)日：2024-03-14

申请号：US18510370

申请日：2023-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31111

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

公开(公告)号：US20220384442A1

公开(公告)日：2022-12-01

申请号：US17885383

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.

公开(公告)号：US20210035806A1

公开(公告)日：2021-02-04

申请号：US17074110

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20200161240A1

公开(公告)日：2020-05-21

申请号：US16722630

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L21/3105 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  C23C16/34 ,  C23C16/04 ,  C23C16/02 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20200135590A1

公开(公告)日：2020-04-30

申请号：US16412007

申请日：2019-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.

公开(公告)号：US20170352762A1

公开(公告)日：2017-12-07

申请号：US15226321

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu YANG ,  Kai-Hsuan LEE ,  Sheng-Chen WANG ,  Sai-Hooi YEONG ,  Yi-Fang PAI ,  Yen-Ming CHEN

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.

公开(公告)号：US20160240651A1

公开(公告)日：2016-08-18

申请号：US14622180

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kai-Hsuan LEE ,  Cheng-Yu YANG ,  Hsiang-Ku SHEN ,  Han-Ting TSAI ,  Yimin HUANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L21/0223 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/495 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/802

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack over a portion of the fin structure, and the fin structure includes an intermediate portion under the gate stack and upper portions besides the intermediate portion. The semiconductor device structure further includes a contact layer over the fin structure. The contact layer includes a metal material, and the upper portions of the fin structure also include the metal material.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的半导体衬底和鳍状结构。 半导体器件结构还包括在鳍结构的一部分上的栅极堆叠，并且鳍结构包括在栅叠层下方的中间部分和除了中间部分之外的上部。 半导体器件结构还包括在鳍结构上的接触层。 接触层包括金属材料，翅片结构的上部还包括金属材料。